Quad Core Battle, Intel Yorkfield vs AMD Altair
Joe writes "Yorkfield Extreme Edition based on the 45nm Penry core architecture will meet
heads-on with AMD Altair based on the 65nm K8L core in Q3 2007 as
reported by VR-Zone. Due to its
advanced 45nm process technology, Yorkfield XE is able to pack a total of 12MB
L2 cache (2 x 6MB L2) and still achieving a much smaller die size and higher
clock speed of 3.43-3.73Ghz. Yorkfield will feature Penryn
New Instructions (PNI) or more officially known as SSE4 with 50 more new
instructions. Yorkfield XE will pair up nicely with the
Bearlake-X chipset supporting DDR3
1333, PCI Express 2.0 and ICH9x coming in the Q3 '07 timeframe as well."
I for one... Will... wait for those 80 core CPU's intel said they will have in a 'few' years. I'll refuse to upgrade till I get one! :D
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I've said it before, I'll say it again: This is exactly why competition rocks. Soon, we'll say Moore was no prophet, he was a pessimist!
Ok, so we have all this neat info about the Intel chip; what about the AMD processor (it gets a whole sentence and a half)? If this is supposed to be a "battle", it seems that most of the comparison has already been done in favor of Intel before the event even takes place, if this article is any reference. :P
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Intel is going to need that HUGE cache because of it's limited FSB. It will be interesting to see how they do side by side.
The AMD with it's Hyper-transport could have an advantage over the Intel chip but right now it is all pie in the sky.
I wish that AMD had access to the Intel Fab tech. Just how fast and low power would their chips be if they where 65nm right now like Intel's?
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I've often wondered, what are these new instruction Intel keep thinking up? Are they some sort of fancy array processing, new addressing modes? I'm curious. Whatever happened to RISC?
That's because Intel is cheating. They don't have a quad-core die, they have two dual core dies shoved onto a multi-chip package. Each die has a shared 6MB cache.
I mean, frankly... isn't 12MB L2 overkill? We're barely putting today's 2-4MB to good use.
Are you kidding me? With a 4-way superscalar processor running at 3GHz, any cache miss can result in the processor being completely idle for 50-100ns. At an aggressive 50ns memory latency, this is up to 600 wasted opportunities to retire instructions.