PCI SIG Releases PCIe 2.0

symbolset notes that The Register is reporting that PCI SIG has released version 2.0 of the PCI Express base specification: "The new release doubles the signaling rate from 2.5Gbps to 5Gbps. The upshot: a x16 connector can transfer data at up to around 16GBps." The PCI-SIG release also says that the electromechanical specification is due to be released shortly.

Comments

Yay

[Anonymous Coward]

Now I can play games at 600fps- I've so been needing the boost- 200fps just doesn't cut it.

But seriously- the data acquisition and video rendering markets should benefit from this. Cool.

Re:Yay

[killa62]

yes, but will it run duke nukem forever?

Re:Yay

[Anonymous Coward]

Well, this card might be up to the task.

Re:Yay

[jandrese]

The thing about 120FPS is that when someone is quoting you that number, they're talking about the framerate when you're sitting in the entrance room after first booting up the game. In complex environments where you have lots of monsters and particle effects on the screen, that number can quickly drop down into the 30-60 range. While this is still more than playable, if you'd only started at 60 or 45FPS the game would bog down in the difficult sections (and those sections are typically where you need that extra accuracy and quicker response time).

Graphics get easier and easier to render

[scwizard]

Slower than they get easier to create.

Confusing article texts...

[RuBLed]

The signalling rates are measured in GT/s not Gbps (correct me if I'm wrong). The new release doubles the current 2.5 GT/s to 5 GT/s. As a comparison, the 2.5 GT/s is about 500 MB/s bandwith per lane thus 16 GB/s in a 32 lane configuration.

I tried to do the math but I just can't get it right with Gbps instead of GT/s.

http://www.intel.com/technology/itj/2005/volume09i ssue01/art02_pcix_mobile/p01_abstract.htm

Re:Confusing article texts...

[Kjella]

It's 2.5 and 5.0Gbps, but with a 10 bits to encode 1 byte (8 bits), so net 250MB/s to 500MB/s, which works out to 16GB/s in a 32-lane config. "The upshot: a x16 connector can transfer data at up to around 16GBps." in the article is simply wrong.

Re:Confusing article texts...

[SQL Error]

I have no idea why they'd do it, but they're probably adding the upstream and downstream bandwidth to get the 16GB/s figure.

Because it gives a bigger number.

Re:Confusing article texts...

[grindcorefan]

Well, one 16x link can transmit 8 Gibibytes per second. As PCIe is full-duplex, stupid salesdroids and marketingdwarves can be expected to simply add both directions together and use that figure instead. But I agree with you, it is misleading.

PCIe 1.0 does 2,500,000 Transfers per second per lane in each direction. Each transfer transmits one bit of data.
It uses a 8B/10B encoding, therefore you need 10 transfers in order to transmit 8 bits of payload data.
Disregarding further protocol overhead, the best rate you can get is 250,000,000 bytes of payload data per seconds per lane.
16 * 250 * 10^6 = 4 * 10^9 = 4 Gibibytes/s on a 16x link in each direction

with PCIe 2.0 the data rate doubles, therefore the max transfer rate per direction is 8 Gibibytes per second on a 16x link in each direction when you disregard protocol overhead.

Sigh

[Umbral Blot]

I know this is news, and actually relevant to /. (for once), but I find it hard to care. Sure the specification is out, but it will take a long time I suspect to find its way into computers (since the existing version is so entrenched), and even longer for cards to be made that take full advantage of it. Is there something I am missing that will make this new standard magically find its way into computers in the next few months? Do I have to turn in my geek card now?

Re:Sigh

[Indy1]

its a good thing. By getting the standard approved way before its needed, it gives everyone (hardware oem's, os developers, etc) plenty of time to integrate support for it. Rushing critical standards like this leads to nasty problems (think VLB) or outright non adoption.

When the ATA standards 33, 66, 100, etc, were adopted, everyone was saying the same thing - why in the hell is it needed. But by getting it adopted and published before it was needed, it gave all the chipset and motherboard vendors time to build it in their products. Result - in the past 10 years hard drives have NOT been bottlenecked transferring data between the drive and motherboard. You can get a screaming fast hard drive, stick it in an older motherboard (say with in 2-3 years of the hard drive's date), and it almost always works without issues.

Pci-e 1.0 took too long to come out. The Pci bus has been overwhelmed by modern video cards (which led to the AGP hack, which fortunately worked fairly well), scsi and raid controllers, ethernet cards (pci cant even give a single gig nic enough bandwidth), usb 2.0, firewire 400 and 800, etc etc etc. Pci-X was complex, expensive, and not widely available. It also ate up too much of the motherboard real estate.

By getting on the ball with Pci-e 2.0, we won't see the same problem again for a while. Now only if firewire 800 and e-sata could be more common........

Re:Sigh

[evanbd]

Well, it's back-compatible with PCIe 1.0 and 1.1, so it aside from price there's on disadvantage to including it. Whether there's demand for it is another question, but I'm sure the graphics card makers will find something to do with it. Think back to AGP 2x/4x -- those made it onto cards and motherboards fairly quickly, iirc.

Re:Sigh

[mabinogi]

I'd assume it'd be backwards compatible, similar to the AGP standards - in most cases you could stick any AGP card in an AGP 8x slot (as long as the motherboard still supported the voltages used by the older AGP versions, which was true in most cases).

If that's the case, then there's no barrier to adoption and manufacturers can just start cranking them out as soon as they're ready. It's only when a technology requires a completely new platform at multiple levels that adoptions is slow, and that was why PCIe took so long.

Nothing beats GPU in the CPU

[suv4x4]

It'll be interesting to compare the performance of the built-in GPU unit in the new Fusion AMD processors, and the latest PCIe.

That said, of course PCIe has more applications than hosting a GPU card.

Re:Nothing beats GPU in the CPU

[suv4x4]

Not really. AMD's primarily targeting the mobile market with Fusion

And...? I use a laptop, for example.

Also multiple CPU-s was primarily targeting the server market.. but look at the processors now. Two fully functional CPU cores in one processor, even for non-pro desktop machines.

Who cares!

[winchester]

2.5 to 5 Gb is still "only" 250 to 500 MB (roughly). My SGI Octanes could do that 7 years ago! (And still do that regularly, for the record). So what's the fuss?

Re:Who cares!

[prefect42]

Anyone who pretends octanes are high performance (or even *were*) needs help. And I've got a pair in the cupboard.

Fantastic news!!

[waynemcdougall]

This is a firmware upgrade, right?

Next few months? How about Q3?

[kinema]

Intel is scheduled to start shipping their X38 (aka "Bearlake") chipsets Q3 of this year. The final v2 spec may have just been released but it's been in development for sometime allowing engineers to at least rough out designs. Also, much of the logic from previous v1.x chipsets can be reused as v2 is an evolution not a completely new interconnect standard.

Re:Why 'PCI'?

[Andy Dodd]

It has more to do with PCI than you think.

While the electrical interface has changed significantly, the basics of the protocol have not changed much at all, at least at a certain layer.

The end result is that at some layer of abstraction, a PCI-Express system appears identical to a PCI system to the operating system (as another poster mentioned). BTW, with a few small exceptions (such as the GART), AGP was the same way. Also, (in theory) the migration path from PCI to PCI Express for a peripheral vendor is simple - A PCI chipset can be interfaced with a PCI Express bus with some "one size fits all" glue logic, although of course that peripheral will suffer a bandwidth penalty compared to being native PCIe.

Kind of similar to PATA vs. SATA - Vastly different signaling schemes, but with enough protocol similarities that most initial SATA implementations involved PATA-to-SATA bridges.

Re:Math???

[onemorechip]

80 Gb/s would be the half-duplex bandwidth. Full duplex is 160 Gb/s (if you can find an application to utilize all of both directions). PCIe uses an encoding of 10 bits to the byte, for numerous technical reasons but primarily to maintain a DC balance (50% ones, 50% zeros) and to ensure maximum run lengths so that the clock (embedded in the serial stream) can be recovered at the receiving end. 160/10 = 16 GB/s.