Intel 45nm Fab Process Launched And Penryn Preview

NinjaKicks writes "Intel has decided to make public details of their new 45nm manufacturing process and also has broken news that next-gen Penryn core processors are running various versions of Windows and Vista successfully. Penryn will offer a host of core tweaks over Conroe, larger cache sizes, and SSE4 support. Also, although clock speeds will be increased, processors based on Penryn should fall within the same thermal power range as Conroe. Word is Penryn will also be compatible with some of the existing motherboards on the market while others will need either a BIOS update or perhaps other board-level changes."

Comments

Is this a major breakthrough?

[kestasjk]

• ~2x improvement in transistor density, for either smaller chip size or increased transistor count
• ~30% reduction in transistor switching power
• >20%improvement in transistor switching speed or >5x reduction in source-drain leakage power
• >10x reduction in gate oxide leakage power

As a layman this sounds like a pretty massive improvement. Is this a major breakthrough or is this progress as usual?

Re:Is this a major breakthrough?

[RicktheBrick]

If one has a penny and doubles it one has $.02. If one has a million dollars and doubles it one has 2 million dollars. Most people would consider the latter to be a more important improvement. It is the same for microprocessors, doubling now is that much greater than it was 30 years ago.

Re:Is this a major breakthrough?

[Bender_]

This is the first time since 1969 that a major modification to the MOSFET gate stack occured. In fact it is fairly major. I should remind you that this is a structure that is replicated around 1e19 times each year and is responsible for the biggest part of the 270 Billion US$ semiconductor market.

At least ten years of work in academia and industry and billions of dollars were poured into this. Intel is the first company to make the move and introduce high-k.

(Yes, there were a few minor modifications to the SiO2/Poly stack in between: Plasma nitridation and numerous improvements on SiO2 growth)

Re:Is this a major breakthrough?

[Bender_]

That is not entirely correct. Intel had basically maxed out SiON previously, I doubt they could have gained that much in performance without high-k.

Re:Can we see some clock speed advances?

[cp.tar]

Can I see the clock speed boosted? Not everything can be parallelized and besides I don't think anyone at Microsoft knows how to.

Who knows, maybe we're looking at the days of assembly programming again... you know, the days of well-written, optimized software?

The ever-growing processor speed had all but removed the need for optimization; maybe the long-forgotten art is facing a revival...

Still on the FSB

[Joe The Dragon]

If you are going to the make the chips smaller how hard is it to come out with a true quad-core?
Havening 2 duel-cores linked by a fsb bus will get in the way even faster as the speed of the cpu gets higher.
And a 4 cpu quad-core sever will likely choke up at the chipset to ram link as well as the chipset to chipset link.

Also if your duel quad-core workstation only have has the pci-e lanes for 1 x16 slot and the 8 other ones are used for the chipset to chipset link amd based ones will blow it away even more so with KL8 cpus. Right now an 2 cpu amd board has 4 pci-e x16 slots running at x16 x8 x16 x8 with 2 x4 lanes left over + each cpu can have a HTX slot or other HT based chip hook up to it.

FTFA

[Aaron England]

This is a show of strength if you will, and an impressive one at that. How impressive? We'll wrap-up here with a few quotes from Gordon Moore (Intel), Professor Dimitri Antoniadis (MIT), and Yoshio Nishi (Stanford) telling you what they think of Intel's achievements.

"The implementation of high-k and metal gate materials marks the biggest change in transistor technology since the introduction of polysilicongate MOS transistors in the late 1960s" - Gordon Moore

"The Intel 45-nm CMOS technology marks a historic milestone for the semiconductor industry. Similar to the transition from single metal (Al) gate to polysilicon gate that has allowed optimal nFET and pFET design, the introduction of dual metal with high-k-insulator gate-stack opens the path for optimal design of both types of FETs, at insulator thicknesses necessary for continuing device scaling that are impossible to reach with the industry-standard silicon-dioxide-based insulators. Many options of high-k gate-stacks have been the target of intense industry and academic research for many years now, but Intel's demonstration of a manufacturable dual-metal/high-k solution is a remarkable first." - Prof. Dimitri Antoniadis

"It is a huge break through to replace more than three decade's long successful polysilicon gate technology with a new high-k+metal gate technology. Though the combination of high-k dielectrics and metal gate electrode for advanced CMOS has been extensively studied by many researchers around the world as the ideal MOS gate structure, the technical hurdle to bring the technology to manufacturing floor has been believed still too high for the 45nm node. As a researcher in this field, I am pleasantly surprised by the announcement and would like to congratulate Intel researchers for their success that Intel has demonstrated 45nm microprocessors with their high-k and metal gate technology. Even though specific metal and high-k material have not been disclosed at this moment, this is a revolutionary step toward the world of sub-50nm CMOS integrated circuits, as this new technology will drastically improve transistor performance in all fronts of electrical specifications, resulting in significant improvement of IC performance." - Yoshio Nishi

Re:FTFA

[stevesliva]

"The implementation of high-k and metal gate materials marks the biggest change in transistor technology since the introduction of polysilicon MOS transistors in the late 1960s" - Gordon Moore

I don't know, I may have to disagree with his eminence on this one... but, parsing his statement a little more finely, he does specifically mention transistor technology. I still view this as an evolutionary refinement of CMOS, and not as big as the transition from bipolar to CMOS for mainstream processors. It is a bigger deal than strained silicon. And by specifying "transistor" he of course sidesteps the comparision to the similar chemical reengineering of the back-end metal stack that came with the introduction of copper and low-k dielectrics. I speculate that like those changes, though, the implementation of the process changes will be relatively transparent to the circuit designers. Yes, the models change, hopefully the subthreshold leakage goes way down, but you've still got the G,D,S,B paradigm... right?

Re:high capacitance

[WhiplashII]

In a CMOS-like technology, you want overall capacitance as small as possible - because you have to charge and discharge that capacitor once per cycle. A first order approximation of power used is 0.5*Capacitance*(voltage squared). A first order approximation of the speed of the device is voltage*current/capacitance (where current is an exponential function of voltage). This means that from a circuit perspective, capacitance is the root of all evil (it both slows you down and uses up power).

When you look at it from inside the device, things change. Transistors work by having the gate-channel capacitor charge up and discharge. You need a certain amount of capacitance for it to work. An easier way to look at it might be to consider the electric fields instead of capacitance. A high K dielectric concentrates the fields in the channel instead of inside the gate oxide. This way, the fields are applied where they are useful (the channel) instead of where they are unneeded (the gate oxide). Obviously, this is somewhat of a simplification, but hopefully you get the gist of it - the capacitance is necessary inside the device, and by using a high-K dielectric you can concentrate that capacitance where you need it.

IBM and Intel both a anounced major breakthrough

[ysegalov]

You are missing the point here. IBM and intel, on the same day (Friday), independently announced a breakthrough in transistor design. Now isn't this strange? The biggest advance in transistors in the last 40 years or so - and two different companies announce it on the same day?!?!? Fishy.

Error in TFA

[dreddnott]

The article linked above refers to "Halfnium", with is both an element that does not exist and a gross misspelling of Hafnium , which is the new High-K replacement for silicon dioxide. It's also worth pointing out that both IBM and Intel announced this breakthough almost simultaneously, and AMD will reap the windfall benefits through its own partnership with IBM (they will move to the 0.45 process some time in 2008). AMD has also announced a low-K breakthrough that they will be implementing in their 0.65 process as well.

To give Intel sole credit for this breakthrough might be a little inaccurate.

Re:2.13 Ghz dual versus 4.5 Ghz

[init100]

They may give us 8 cores at 4 Ghz instead .. but that's cheap crap, you can bet the compilers and apps for it will be donkey inefficient. I hope a competitor realizes the importance of instructions per second.

I hope you realize that there are some physical limits and constraints that cannot be broken, or can be broken at a massive disadvantage for other parameters. If I don't remember wrong, power consumption and therefore heat emission is proportional to the square or even the cube (at least nonlinear) of the clock speed at a certain manufacturing process. So you might have a 33 GHz processor (10x speed increase compared to what we have today) but the power consumption would increase from about 100 watts to 10 kilowatts. Not only would this bring a hefty increase in your power bill, imagine the cooling system required and the noise output.

An additional problem would be leakage current, since it increases with clock speed (or I'd rather guess it increases with temperature, which is a function of the clock speed). Too much leakage current, and the processor will cease to function. Leakage means that charges will not only travel along conductors, but jump between nearby conductors. Leakage not only increases with clock speed and temperature, but also with line density on the chip. The smaller the components, the larger the leakage at the same clock speed and temperature output.

I might be wrong in the details, but I think most of it is right.