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AMD Athlon 64 6000+ Launched And Tested

Posted by Zonk on from the kicking-the-tires-lighting-the-fires dept.

Spinnerbait writes "AMD officially launched their next speed bump in the Athlon 64 product line, in the form of a new 3GHz part branded the Athlon 64 6000+. This new dual-core Athlon 64 sports 1MB of on-chip cache per core and is designed for AMD's Socket AM2 platform. This chip is still built on AMD's 90nm fab node and is comprised of some 227 million transistors. It also carries a thermal power profile of about 125Watts. Unfortunately, in all the benchmarks seen here, it was still unable to catch Intel's Core 2 Duo E6700 chip at 2.66GHz."

4 of 156 comments (clear)

  1. DOS by Short+Circuit · · Score: 5, Interesting

    I've always wanted to try running DOS on a processor with 1MB of L2 cache...there's just something retro wicked about running an OS where the entire base memory fits in on-die cache.

    I have to wonder if qemu and the kernel's kvm will allow me to dedicate an entire core to a DOS image.

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    1. Re:DOS by ArcherB · · Score: 4, Interesting

      I have to wonder if qemu and the kernel's kvm will allow me to dedicate an entire core to a DOS image.

      Or you could just boot off of a DOS formatted USB key. I remember hearing that the Athlon64 would run all OS's down to DOS 2, I believe.

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  2. Re:Unfortunately? by Machtyn · · Score: 3, Interesting

    It's unfortunate to AMD and those who would support AMD. The customer gets a hotter, more power hungry processor, that is probably just as, if not more, expensive than a cooler, slower GHz rated Intel processor that outperforms the Athlon.

  3. You make incorrect assumptions by lcnxw · · Score: 4, Interesting

    The design and development of a processor has improved vastly since the days of borked multipliers. There are standard benchmark tests that engineers use to rate their designs in-house. If AMD chooses to go with smaller caches, I would imagine they have very good reasons.

    Perhaps in order to keep good performance when communicating between caches they need to keep the number of memory addresses low so that the overhead stays low. They decided that separate caches was a better model, and they currently have to maximize performance with this design.

    AMD might have favored their server market when choosing this design and separate cache works better for server machines. They may need to refine their architecture for the desktop market. Don't be so quick to accuse AMD of making cache mistakes without doing the math for find the theoretical best solution.