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IBM Heralds 3-D Chip Breakthrough

Posted by kdawson on from the more-moore dept.

David Kesmodel from WSJ writes to let us know about an IBM breakthrough: a practical three-dimensional semiconductor chip that can be stacked on top of another electronic device in a vertical configuration. Chip makers have worked for years to develop ways to connect one type of chip to another vertically to reduce size and power use. The IBM technique of "through-silicon vias" offers a thousand-fold reduction in connector length and a hundred-fold increase in connector density. The new chips may appear in cellphones and other communication devices as soon as next year. PhysOrg has more details.

5 of 99 comments (clear)

  1. Very nice, but... by Rosco+P.+Coltrane · · Score: 2, Interesting

    Chip manufacturers have better define some kind of common norm for the Vccm Vss, GND, busses, etc... pins on similar devices (like ICs, RAM chips and such), otherwise it's back to square one with a circuit board that has to pick up the lines and reroute them to other components, and the advantage of this technology would be zilch.

    --
    "A door is what a dog is perpetually on the wrong side of" - Ogden Nash
    1. Re:Very nice, but... by stevesliva · · Score: 3, Interesting

      otherwise it's back to square one with a circuit board that has to pick up the lines and reroute them to other components, and the advantage of this technology would be zilch.
      There is no implied change in the chip packaging that is the interface to a circuit board. There are already plenty of packages that have two chip dice side-by-side. This will just stack the dice on top of each other within the package.
      --
      Who do you get to be an expert to tell you something's not obvious? The least insightful person you can find? -J Roberts
  2. I wonder how they will cool this? by LiquidCoooled · · Score: 4, Interesting

    Surely they need to cool the components in the middle of the stack?
    Unless they decide to leave some of the holes open then anything in the middle is going to overheat?

    I always imagined this kind of tech running on some kind of multi layered wire fence with plenty of room for cooling.

    Incidentally, didn't Hitachi beat them to the whole 3d element thing?
    http://www.hitachigst.com/hdd/research/recording_h ead/pr/PerpendicularAnimation.html

    --
    liqbase :: faster than paper
    1. Re:I wonder how they will cool this? by s-gen · · Score: 3, Interesting

      It looks like they might be planning to pump liquid between the layers:

      http://www.zurich.ibm.com/st/cooling/integrated.ht ml

  3. Re:Heat by Jake73 · · Score: 2, Interesting

    Heat is certainly a concern. However, vertical stacking also helps address the issue of disparate technologies. For example, you may have two ICs that are manufactured with, say CMOS and bipolar technologies that together won't generate enough heat to be a concern, but because they are different technologies, need to be separated and therefore take up more space.

    On the other hand, it would be neat to see them put heatsinks between each individual chip. They could still drill and insert the tungsten vias through the heatsink. The heatsinks would probably need to be pretty advanced, though, to move the head to the fringes. Maybe a circulating fluid or something.