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IBM Heralds 3-D Chip Breakthrough

Posted by kdawson on from the more-moore dept.

David Kesmodel from WSJ writes to let us know about an IBM breakthrough: a practical three-dimensional semiconductor chip that can be stacked on top of another electronic device in a vertical configuration. Chip makers have worked for years to develop ways to connect one type of chip to another vertically to reduce size and power use. The IBM technique of "through-silicon vias" offers a thousand-fold reduction in connector length and a hundred-fold increase in connector density. The new chips may appear in cellphones and other communication devices as soon as next year. PhysOrg has more details.

8 of 99 comments (clear)

  1. More information by karvind · · Score: 4, Informative
    As article says they had been working on it for a long time, they had published few details before.

    http://www.research.ibm.com/journal/rd/504/topol.h tml

    http://domino.watson.ibm.com/comm/pr.nsf/pages/new s.20021111_3d_ic.html

  2. I wonder how they will cool this? by LiquidCoooled · · Score: 4, Interesting

    Surely they need to cool the components in the middle of the stack?
    Unless they decide to leave some of the holes open then anything in the middle is going to overheat?

    I always imagined this kind of tech running on some kind of multi layered wire fence with plenty of room for cooling.

    Incidentally, didn't Hitachi beat them to the whole 3d element thing?
    http://www.hitachigst.com/hdd/research/recording_h ead/pr/PerpendicularAnimation.html

    --
    liqbase :: faster than paper
    1. Re:I wonder how they will cool this? by SQL+Error · · Score: 4, Informative

      You wouldn't be able to stack multiple desktop CPUs, because it would generate too much heat. But you could stack a CPU on top of its own level 2 cache instead of next to it, making for shorter wires and a faster chip. Or stack a GPU on top of DRAM, so that you could have a 2048-bit bus instead of 256-bit.

      Then they just rely on the upper layer to conduct enough heat to keep the low layers cool.

    2. Re:I wonder how they will cool this? by duncanFrance · · Score: 5, Informative

      There are some thermal advantages to this sort of interconnect. Since it keeps the wirelength short it means the drivers don't have to be so powerful. Hence a fair amount less heat will be generated. Driving any amount of capacitance at GHz speeds wastes shed-loads of power.

      Average power dissipated = V*V * f * C

      So reducing V obviously makes a big difference (hence partly why operating voltages of ICs decrease with frequency), but getting C down will help also.

  3. What?????? by Xinef+Jyinaer · · Score: 5, Funny

    The chips didn't exist as 3-D objects prior to this? Infact, wouldn't a chip that only exists in two dimensions be much more difficult to make?

    --
    Some days I just get bored and Troll post all the memes I can think of...
  4. They told us not to ask where they got it. by illegalcortex · · Score: 4, Funny

    It was scary stuff, radically advanced. It was shattered... didn't work. But it gave us ideas. It took us in new directions... things we would never have thought of. All this work is based on it.

  5. New Operating System Required For 3d chips by crea5e · · Score: 5, Funny

    LEG-OS. 64 block architecture. Also themeable for star wars and lord of the ring fanboys.

  6. Well by ShooterNeo · · Score: 4, Informative

    This is it. Maybe. Possibly major problems with heat dissipation. However, there are some massive advantages :

    1. One tradeoff IC designers always face is that the fastest, lowest latency access is always to on-die components. On-Die memory (cache) is almost ALWAYS faster, coprocessor interconnects (like for dual core) are far quicker, ect. With any given level of state of the art, you can get a much higher clock signal over itsy bitty paths on silicon from one side of the chip to the other than going out to big, clunky, exremely long wires.

    2. The tradeoff is that a bigger chip radically reduces yields : the chance of a defect causing a chip to be bad goes up with the square of the number of gates.

    3. This technology allows one to use multiple dies, and to interconnect them later. There's just one problem.

    HEAT DISSIPATION. A 3d chip will of course have it's heating per square centimeter multiplied by the number of layers. The obvious solution, internal heatpipes, has not yet been shown to be manufacturable.

    Hence TFA mentioning use in devices such as cell phones, where bleeding edge high wattage performance is not a factor.