AMD Releases Image of Phenom/Barcelona Die
MojoKid writes "A few weeks ago, AMD
released information on new branding for their desktop derivatives of the Barcelona core, now dubbed the Phenom FX, X4 and X2. If you're unfamiliar with Phenom, the processors will be based on AMD's K10 architecture. They've been tight lipped about specifics, but we know that it will feature a faster on-die memory controller, support 64-bit and 128-bit SSE operations, and they'll be outfitted with 2MB of on-chip L2 cache (512KB dedicated per core) in addition to 2MB of shared L3 cache. This week, instead of revealing some more of the juicy details regarding those enhancements, AMD just sent over a tasty photo of a Phenom die. At least it's something."
can you see how fast it is? How about some specs we understand?
On-chip connectivity can be much broader and lower-latency than off-chip connectivity. The two-dual-core in one package "quad cores" of Intel have to talk via the off-package north bridge. As you can see from the AMD Barcelona/K10/10h snapshot, the cores live together on a single piece of silicon.
The space between the the cores is a very broad crossbar, allowing fast inter-core synchronization/cache-coherency. The uniform block at the edge of the chip, outside the cores, is the L3 cache shared by all four cores. Each core has its own L1 and L2 cache. This design is nicely symmetric: each core has equivalent resources. It should do very well on heavy-duty symmetric multiprocessing applications.