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Supercomputer On-a-Chip Prototype Unveiled
An anonymous reader writes "Researchers at University of Maryland have developed a prototype of what may be the next generation of personal computers. The new technology is based on parallel processing on a single chip and is 'capable of computing speeds up to 100 times faster than current desktops.' The prototype 'uses rich algorithmic theory to address the practical problem of building an easy-to-program multicore computer.' Readers can win $500 in cash and write their names in the history of computer science by naming the new technology."
Assuming this actually works as detailed and the fine print on the claim isn't too onerous, there's three practical problems:
:) Maybe by the time this is a viable commercial product it will have more practical uses. (Remembering LOGO on my TI-94/A... we've come a long way baby)
1. Many applications are limited by the speed of the user, not the computer. You can only type or click so fast.
2. Hardware would have to catch up to drive this beast. This would max out all known memory and storage systems. Not to mention your internet connection.
3. As has been mentioned time and again, until developers actually embrace multi-threading this will be relatively useless. Tests from various hardware sites have shown that going from the Core 2 Duo to the Core 2 Quad offers very little benefit except for a very small subset of users... who should probably be running workstations anyway (Video editing, 3D rendering, etc.)
However, I have a ton of HD content on my MythTV box that I would like to turn this processor and h264 loose on
Well, you should learn to follow links.
It was quite easy from the article to find more information about the project.
Sorry, teleporters just kill you and then make a copy. A perfect, soul-less copy.
You know, autovectorization looks good on paper. But for most tasks, it really doesn't net you any benefit unless you can separate all your work into non-overlapping chunks. You can't have any interdependancies on your working set (or risk expensive, non-scalable locking), and if you're all pulling from a single data source to split up the analysis work you'll spend a lot of time in contention for the pipe to that resource.
For example, it wouldn't make searching a database (scratch that, searching any data set) any faster unless the index was already pre-split among the processing units.
In this architecture the processing units have the same bus to RAM and disk on the front and back ends and have to deal with contention.
Your system is only as fast as the slowest serial part. Typically this is storage media, a network connection, or a memory crossbar. Processors really are fast enough for the non-embarrasingly parallel stuff. They are at the right ratio with respect to the other slower busses to do most general purpose work.
If you want to do more than that then its other things; storage media, memory, I/O busses -- that need to be multiplied in density and number. Only then can we see higher throughput.
Autovectorization is only good for things we already have offloading for anyway (TCP encryption, graphics, sound)... and for those general purpose cases like in Game AI where you might want a linear algebra boost NVidia has beaten these guys to the punch with the GP stream processing in the newest chips and the very flexible Cg language/environment.
THIS THING CAN TURN ON A DIME, MACROSSZERO STYLE ALSO FUCK BETA, ~NYORON
Actually power consumption per instruction has remained pretty constant over the years if you exclude the Pentium 4. The Yohah uses about the same amount of power per instruction as the Pentium. So if you are running 100 times more instructions per second, well you will be using 100 times more energy.
Sun had something with tiny radio interconnects between chips. This way, they could have thousands of "pins" on the chip and the only metal pins you would need would be power and ground. If I remember correctly, I had a server whose memory had to be upgrades about 8 (or 9) modules-with-lots-of-pins a time, so, wide buses are nothing new.
Intel also had something about optical interconnects, which are also nice, since you can place your "connectors" anywhere in the chip and not just around the borders and, if you can aim properly, the receivers can be much smaller than the pads around a current chip (or, by properly spreading the signals, one could synchronize many receivers to a single source very efficiently).
We may not be constrained by the number of pins a connector has for that much longer.
http://www.dieblinkenlights.com
Anyone remember the hype of the i860? Great on paper, but not so great in reality. I really hope this works though, von Neuman architecture was always supposed to be a stop-gap (even vN said so I think).
Bitter and proud of it.