MIT Focuses on Chip Optimization

eldavojohn writes "MIT's Microsystems Technology Laboratories is focusing on the manufacturing of chips as the variables that affect chip quality become more and more influential. From one of the researchers, "The extremely high speeds of these circuits make them very sensitive to both device and interconnect parameters. The circuit may still work, but with the nanometer-scale deviations in geometry, capacitance or other material properties of the interconnect, these carefully tuned circuits don't operate together at the speed they're supposed to achieve.""

Comments

harder on designers

[drakyri]

This isn't really anything new - shrinking design processes always make life harder for designers. Each design process (.25 um, 90 nm, etc.) has a set of rules about things - for example, how close interconnects can be to each other without causing interference.

The ruleset for quarter-micron was maybe forty pages. The ruleset for 90 nm was the size of a small phonebook. I don't even want to think about what the rules for 65 or 45 nm must look like.

Re:harder on designers

[John Betonschaar]

Exactly. As a matter of fact I work for a company (not mentioning which, my boss wouldn't appreciate it) that develops software to migrate chips to smaller technologies, detects/fixes design-rule violations, detects/fixes litho hotspots, that kind of stuff. It is used by many well-known names in the IC industry. We've been in business for more than 10 years already, so this hardly sounds as something new.