MIT Focuses on Chip Optimization

eldavojohn writes "MIT's Microsystems Technology Laboratories is focusing on the manufacturing of chips as the variables that affect chip quality become more and more influential. From one of the researchers, "The extremely high speeds of these circuits make them very sensitive to both device and interconnect parameters. The circuit may still work, but with the nanometer-scale deviations in geometry, capacitance or other material properties of the interconnect, these carefully tuned circuits don't operate together at the speed they're supposed to achieve.""

Comments

Not just lithography

[cannonfodda]

This isn't really that new. There are folk who have been looking at characterising nano-scale variability for years, and there is a LOT more to it that just the fluctuations introduced by lithographic limits. Glasgow uni's device modelling group. What's odd is that these guys are estimating the fluctuations based on mathematical models when there is pretty good data available for the 65nm technology node already.

Re:In Soviet Russia

[Plammox]

It's more likely they'll contribute to increasing the yield from each manufactured wafer, making the maybe not so crazy fast desktop processors cheaper. Also, the material and chemical usage will decrease per "good" cpu die, so there's an environmental angle here, which isn't bad either, I suppose.

Just to clarify

[tygerstripes]

This work is for RFICs (communication chips), not your 10-Core Hyperon or whatever. More importantly, what they're doing is indirectly modelling the correlation between various electrical properties of the micro-components in order to optimise design stability prior to manufacture. This has no direct impact on the manufacturing process, but does impact on more fabrication-robust design.

Ultimately this will have a limited impact on your desktop's Giggerhurts, somewhere way down the line, but it's nothing you'll notice and, for most of us, nothing we'll really understand. Unless the mathematical basis of chip-fab optimisation is your field, this isn't going to mean much.

Re:Just to clarify

[imgod2u]

This affects digital chips more than you think. Process variations are a huge problem as we get to smaller and smaller feature sizes. While analog circuits are much more sensitive to variations in threshold-voltage, capacitance and resistance (and cross inductance), keep in mind that all digital circuits are still analog. They are simply interpreted as 1's and 0's.

With this in mind, consider a digital circuit that's driving the output voltage from the voltage of a logical 0 (let's call it 0V) to logical 1 (let's say, 5V for early TTL lovers). That voltage isn't going to rise instantaneously. The time it takes to go from 0 to 5 volts will depend on:

1. The various capacitances of the circuit, both parasitic and device capacitance.
2. Resistance in various circuit elements.
3. Cross-inductance.
4. Threshold voltages for all of the transistors.

Having an accurate model to statistically predict these variations will allow chip designers to better estimate the speed of their digital circuits. So if the target goal of a chip is 10 GHz, they can know, before they commit to silicon, roughly how many chips in a batch will meet that target speed.

Other factors also play in as we get to lower and lower powered chips. With a VDD of 1.0V or below (as in ultra-low-voltage chips), cross-inductance, capacitance on the power rails, etc. can actually affect the stability of a digital circuit. Noise is injected that can turn a voltage that was meant to be a logical 0 into a logical 1. With modern chips turning voltages in regions of the chip on and off, the di/dt problem comes in. Without accurate predictions as to the impedances across the chip, reflections on the power rails can cause a voltage that's higher than VDD and, if the transistors weren't designed conservatively (to meet power and speed goals), they could burn out.

harder on designers

[drakyri]

This isn't really anything new - shrinking design processes always make life harder for designers. Each design process (.25 um, 90 nm, etc.) has a set of rules about things - for example, how close interconnects can be to each other without causing interference.

The ruleset for quarter-micron was maybe forty pages. The ruleset for 90 nm was the size of a small phonebook. I don't even want to think about what the rules for 65 or 45 nm must look like.

Re:harder on designers

[John Betonschaar]

Exactly. As a matter of fact I work for a company (not mentioning which, my boss wouldn't appreciate it) that develops software to migrate chips to smaller technologies, detects/fixes design-rule violations, detects/fixes litho hotspots, that kind of stuff. It is used by many well-known names in the IC industry. We've been in business for more than 10 years already, so this hardly sounds as something new.

monkeys

[stranger_to_himself]

I read the title as 'MIT Focuses on Chimp Optimization.'

Thought maybe they'd been having trouble recruiting.