MIT Focuses on Chip Optimization

eldavojohn writes "MIT's Microsystems Technology Laboratories is focusing on the manufacturing of chips as the variables that affect chip quality become more and more influential. From one of the researchers, "The extremely high speeds of these circuits make them very sensitive to both device and interconnect parameters. The circuit may still work, but with the nanometer-scale deviations in geometry, capacitance or other material properties of the interconnect, these carefully tuned circuits don't operate together at the speed they're supposed to achieve.""

Comments

Not just lithography

[cannonfodda]

This isn't really that new. There are folk who have been looking at characterising nano-scale variability for years, and there is a LOT more to it that just the fluctuations introduced by lithographic limits. Glasgow uni's device modelling group. What's odd is that these guys are estimating the fluctuations based on mathematical models when there is pretty good data available for the 65nm technology node already.

Re:In Soviet Russia

[Plammox]

It's more likely they'll contribute to increasing the yield from each manufactured wafer, making the maybe not so crazy fast desktop processors cheaper. Also, the material and chemical usage will decrease per "good" cpu die, so there's an environmental angle here, which isn't bad either, I suppose.

harder on designers

[drakyri]

This isn't really anything new - shrinking design processes always make life harder for designers. Each design process (.25 um, 90 nm, etc.) has a set of rules about things - for example, how close interconnects can be to each other without causing interference.

The ruleset for quarter-micron was maybe forty pages. The ruleset for 90 nm was the size of a small phonebook. I don't even want to think about what the rules for 65 or 45 nm must look like.

monkeys

[stranger_to_himself]

I read the title as 'MIT Focuses on Chimp Optimization.'

Thought maybe they'd been having trouble recruiting.