MIT Startup Unveils New 64-Core CPU

single-threaded writes "Tilera, a startup out of MIT, has announced that it is shipping a 64-core CPU. Called the TILE64, the CPU is fabbed on a 90nm process and is clocked at anywhere from 600MHz to 900MHz. 'What will make or break Tilera is not how many peak theoretical operations per second it's capable of (Tilera claims 192 billion 32-bit ops/sec), nor how energy-efficient its mesh network is, but how easy it is for programmers to extract performance from the device. That's the critical piece of TILE64's launch story that's missing right now, and it's what I'll keep an eye out for as I watch this product make its way in the market. Though there are any number of questions about this product that remain to be answered, one thing is for certain: TILE64 has indeed brought us into the era of 64 general-purpose, mesh-networked processor cores on a single chip, and that's a major milestone.'"

Comments

Oblig...

[Bentov]

No one will ever need more than 64 cores.

Re:Oblig...

[Anne_Nonymous]

Unless you need more than four pieces of toast.

Re:Oblig...

[Ninjaesque One]

When the number of cores equals the hertz, then the number should stop doubling.

Instruction Set

[Lally Singh]

FTA: It's a "MIPS-like ISA with a few important and peculiar features"

I'll be interested to see what they're going to do about making it easier to program. Wire delay's going to be exposed as hops on the on-chip network. IMHO, the toolchain side's far more interesting to me than shoving a bunch of cores together on an on-die network....

Assuming they did anything interesting on the toolchain side.

Re:Instruction Set

[evanbd]

Also FTA: "I'm due to talk to the head of Tilera's software team, which is actually larger than the company's hardware team."

I'll be very curious what their development toolchain ends up looking like, but it seems clear they understand the issue.

Re:Instruction Set

[dfedfe]

FWIW:

""If you have an application written for any multi-core or single processor architecture that's written to work with Linux, you can take it, compile it and have it running on our chip in minutes," he said. "Now, if you want to ratchet up the performance, we provide libraries and interface mechanisms that customers can use to tune code."" from here

Re:Instruction Set

[Mex]

""I'm due to talk to the head of Tilera's software team, which is actually larger than the company's hardware team.""

He must be a really fat guy!

Re:Instruction Set

[FuzzyDaddy]

He must be a really fat guy!

No, he just has a REALLY big head.

Re:Instruction Set

[ultranova]

You're hoping they're doing something to make it easier to program, and I doubt they are. The choke point is rapidly becoming scheduling rather than number of cores.

The solution, of course, is to move away from the imperative programming model to dataflow or functional one. That way the compiler can automatically parallelize the task, instead of the programmer having to do so manually.

Re:Instruction Set

[networkBoy]

The best way, IMHO, is to build a two-layer chip - one layer being RAM, the other being the CPU cores Both those require transistors. You can not stack transistors with any current process technology, physics gets in the way.
A chip is basically built as follows

metal
poly
metal
poly
Si Where the poly is the insulator and metal is the same as traces on a PCB. Just like you can not place components in the middle of a PCB you can not place transistors on top of the metal, it would require a second silicon layer that you could dope transistors into.
While there are some technologies (SOI for example) that may allow this in theory, you start to run into other issues like trying to punch through the insulator in specific areas and with high precision (neither of which is easy), heat dissipation (transistors are transistors, and switching produces heat, doesn't matter if it's an ALU or a SRAM). And finally before someone suggests using the other side of the wafer, how do you connect the two sides? A wafer is *very* thick in the scale we are discussing. It would be like mining a hole through the earth.
More useful would perhaps be distributing L0 cache (register memory) a little more liberally in key areas of the processor, but then addressing gets in the way. In theory having a MCM (multi chip module) with Cache - Processor - Cache so there is ample L3 cache running at core/4 clock may help, but costs get prohibitive.

There is no really good solution to moving data around once you start getting to these kinds of density. Eventually wire delay may be the limiting factor to CPU throughput.
-nB

Re:Instruction Set

[imgod2u]

This has been done. There was an article a while back about IBM being able to drill holes through their wafer to produce an interconnect to a second wafer on the bottom.

Intel did this a swell and redesigned the Pentium 4 on it.

The old method of bonding two wafers also works. Smart censors, for instance, bonds a photodetector material (a semiconductor like InGaAs or InSb) onto the top of a cmos chip. The bonding was very expensive, of course, but it is definitely possible to grow a semiconductor on top of existing metal/polysilicon.

Re:Instruction Set

[imgod2u]

Considering these things are MIPS cores, having C code compile to it wouldn't be hard at all I would say. It's utilizing the mesh network that's the problem.

Until I see some results of dynamically-compiled C code that runs really fast on this thing, I don't see it offering better solutions than, say, an FPGA. The exception would be if this was much lower-powered.

It's not theoretically impossible to do. Instead of treating it like a CPU, treat it like a network with micro-ops treated like packets. Run each sequence of micro-ops through something similar to a global routing algorithm and optimization should be fairly easy. This all, of course, assumes that you have something very parallelizable to begin with, like H.264 encoding.

Re:Instruction Set

[timeOday]

I'll be interested to see what they're going to do about making it easier to program... Assuming they did anything interesting on the toolchain side.

Contrary to the summary and your remark, I'm not sure it's Tile64's problem to bring parallel programming to the masses. First, because many-core chips are already useful (and present no special difficulties) for servers that handle many simultaneous connections - in other words, reducing the space and electricity requirements of server farms. That's a significant market.

Second, parallelism is a far broader problem than this tiny company's single product; it's now a problem for Intel and AMD, too - in other words, for everybody. Any effective solution is highly unlikely to be specific to this particular chip.

Sure, it would be great if these guys (or anybody else) made some breakthrough in parallel programming, but that doesn't appear to be the problem they've tackled. You say shoving together a bunch of cores is boring, but to me replacing a cluster with a single $500 chip would be fantastic.

I am interested how this will stack up to Sun's Niagara chip. 600 MHz is pretty slow nowadays.

bulk pricing

[dfedfe]

Only $435 for 10,000 units. Are there 9,999 people on here who want to go in on that?

Correct! 6000 cores

[Dachannien]

Fry: If only they'd built it with 6001 cores! When will they ever learn!

Now that I have a 64 core CPU...

[HerculesMO]

How do I overclock it?

I Did RTFM, and there's key info missing

[Nova Express]

Key information missing from the article:

1. Die size: How big is it?
   
2. How many watts of power does it consume?
   
3. What is the heat dissipation?
   
4. What is the floating point performance?
   

Without those bits of information, it's impossible to guage exactly who might night this chip, and how successful it might be.

Re:I Did RTFM, and there's key info missing

[trolltalk.com]

The watts isn't missing:

TFA says its between 175 and 300 milliwatts per core - do the math. 12 to 19 watts. They're targetting the embedded market (and with those low power consumption figures, I think a super laptop would be a no-brainer).

Re:I Did RTFM, and there's key info missing

[WindBourne]

here is a bit

Re:I Did RTFM, and there's key info missing

[HerculesMO]

If we are judging based off of current generation processors, I believe the size of the chip will be about 3 feet squared.

Warning: Sarcasm above may cause irritation of skin and explosion of monitor.

Re:I Did RTFM, and there's key info missing

[imgod2u]

Those are *not* very impressive figures for the embedded market. I imagined the whole 64-core chip would run below 100mW. If we're talking 12 to 19 watts for the chip, it is a beast in embedded terms. For reference, an SoC with 4 ARM cores, all of the peripherals that that thing has plus dedicated DSP/FPU units would still be under 4W.

FPGA's (particularly ones from Xilinx) that offer similar logic horsepower (assuming you had a digital designer to write your VHDL for your) for less than 500mW.

The latest Virtex 5 for DSP applications can provide the same processing capability these guys claim (2x H.264 streams) along with all the bells and whistles and on top of that, you have 2 PPC hardcore processors to act as arbitrators for slower functions.

Those things suck up up to 1W though and that's a lot of power for an embedded system.

The real question is

[WindBourne]

Is not if it will run Linux (it will), but if it will run windows? CE does not count.

I'm ready for it

[Anonymous Coward]

On my laptop right now:

> ps aux | wc -l
281

Of course not all those processes are in runnable state. On the other hand, many of those processes have multiple threads. A typical Java Swing GUI app may have a dozen threads, for example. A web server process can easily have dozens of runnable threads. Software is going to take a little bit of catching up, but nothing huge.

Re:I'm ready for it

[Bryan Ischo]

Just as your system has only a few processes that want to be scheduled simultaneously (and so your observation that "not all of those processes are in [a] runnable state" is correct), those Java Swing applications you are talking about very rarely have more than a thread or two wanting to do work at the same time. The web server is a better example of concurrent execution but those are most often I/O limited as much as CPU limited, and in the vast majority of cases the bottleneck is not the number of threads that can execute concurrently.

It's very hard to take advantage of multiple cores because very often, there isn't more than one thing for a program to be doing at the same time, and for most desktop users, there are rarely more than 1 or 2 programs running actively at a time. Many code paths are not explicitly parallelizable, and many more are parallelizable but not easily so. Just as clock speed is not the holy grail of processor performance, core count isn't either.

Rumored...

[SeanMon]

It's rumored to be able to run 16 whole instances of Vista simultaneously!*

*Required 32 GB of RAM not included.

Instruction set?

[Eponymous Bastard]

I can't believe startups haven't figured out that incompatible chips aren't what the market wants. They're either going to sell directly to "supercomputer" makers or just crash and burn.

They'll probably market running Java as a strong point.

(Then again, does it run Linux?)

Re:Instruction set?

[Wesley Felter]

What's the instruction set of your router? Your TV? Why does it matter?

wow.

[paulbd]

it might even be as successful as the similarly revolutionary Kendall Square Research machine, just down the road from MIT.
i wouldn't hold my breath.

Tequila128

[crea5e]

In related news, Boston College has also released a processor of their own.

The Tequila128. Free copy of virtual beer pong included.

But does it...

[niceone]

well, yes it does run Linux - full SMP 2.6 according to the blurb on their site.

Re:But does it...

[Eponymous Bastard]

One thing the blurb doesn't make clear is that this is not a workstation CPU. It's designed for embedded systems and system on a chip applications. They mention video compression as an example.

If you look at their block diagram this looks more like an FPGA-on-drugs than a CPU.

The individual blocks are probably programmed with GCC, since it should be trivial to port it to a MIPS-like architecture. I wonder if the interconnect uses a VHDL type language or if they rely on their weird cache to build efficient shared memory.

Either way, it looks like you have to keep in mind the architecture while designing your software. I doubt they can build a compiler that can manage the division of labor.

Unlike a typical multicore design you wouldn't use this to parallelize a multithreaded application or a multiprocess workload. The center processors will have a very different latency characteristic than the edge ones, and you want the parts that interact with the network to be on the points adjacent to the controllers, for example.

So it should work great for an especially designed system, but not so great as a general purpose CPU

Re:Questions about company

[larry bagina]

it reminds me of another T company -- Transmeta. I wonder if they'll hire RMS to work on HURD....

Tilera MDE

[MrMunkey]

For those of you wondering about what their software will be like, here's some info on their Multicore Development Environment (MDE). http://www.tilera.com/products/software.php It's not the most info in the world, but it's a start.

This was my companys idea in 2001

[John Sokol]

It's was called Enumera www.enumera.com

I started to work with Chuck Moore, the author of the FORTH Language on a 7X7 array of very fast small processors.

From at talk I did, February 16, 2001
From http://www.dnull.com/~sokol/amorp/emtalk.ppt

On this size Chip a 7x7 array (49 CPU's) with ram could be
build. Co-processors could also be added.
Each CPU's would be operating at 2400 MIPS x 49 for a total of 117 Billion operations per second.
The power consumption would be 1 watt 1.8 Volts a 500 mA.
With this level of computing power new applications that were unthinkable before, now become possible. Also mention earlier on Slashdot:
http://developers.slashdot.org/comments.pl?sid=138 584&threshold=0&commentsort=0&mode=thread&cid=1160 0799

And earlier here:
http://www.colorforth.com/ 25x Multicomputer Chip

This eventually became IntellaSys after Enumera failed.

IntellaSys CTO Chuck Moore to Present at In-Stat Spring Processor Forum; Scalable Embedded Array Platform for Implementing Asynchronous, Scalable Multicore Solutions Using Elegant VentureForth Programming to Be Discussed in Detail http://www.intellasys.net/products/24c18/SEAforth- 24A-3.pdf
http://www.findarticles.com/p/articles/mi_m0EIN/is _2005_Oct_24/ai_n15730157
http://www.findarticles.com/p/articles/mi_m0EIN/is _2006_May_1/ai_n16135032

Also for older info see:
Specifically look at the P21 / I21/ F21 chips...

http://www.enumera.com/chip/
http://www.ultratechnology.com/ml0.htm
http://www.ultratechnology.com/f21.html#f21
http://www.ultratechnology.com/store.htm#stamp
http://www.ultratechnology.com/cowboys.html#cm

Re:This was my companys idea in 2001

[John Sokol]

I an not sure really what the point is, I guess I am just venting out of frustration. Also adding some information to anyone interested similar work I had done, showing this isn't a new idea.

I put $100,000 Cash and almost 2 years worth of work into this and got nothing, no one was even interested.
But then I see a Bunch of MIT weenies do it and they get all kinds of attention as something new and revolutionary 6 1/2 years later.

There is also a real chance they took the idea right off my web site or slashdot post or maybe even present at my talk and never even gave me some credit for the concepts. There design really looks like it was lifted straight off my paper.

So I guess at least I am exposing some plagiarisms.

I mean what the heck is the point of having an incredibly good idea and investing so much time and money into it just to watch someone else profit from it without so much as a thank you.

I was at least trying not to whine and complain in my post and keep it purely informative and provide links to my very similar earlier works.

Re:This was my companys idea in 2001

[suv4x4]

I an not sure really what the point is, I guess I am just venting out of frustration. Also adding some information to anyone interested similar work I had done, showing this isn't a new idea.

I put $100,000 Cash and almost 2 years worth of work into this and got nothing, no one was even interested.

I'm not sure why the frustration. I'm sure multi-core was not just your original idea. If you're in the industry you know that:

1. IT is rich on ideas, poor on implementation.
2. Marketing a product is just as (if not more) important than making a product.
3. Most businesses fail in the first 5 years. And this one may be no exception. They didn't exactly enjoy massive success just yet. They got few crappy articles and landed Slashdot. Kind of hard for a hardware company to cash in on that alone.

There design really looks like it was lifted straight off my paper. So I guess at least I am exposing some plagiarisms.

You don't expose plagiarism by venting frustration on Slashdot: where are your patents. How's there guarantee you're the originator, and how's there guarantee they *stole* your work versus reinvent it independently, which happens often with technology that's in a boom (i.e. multi-core designs). There's a reason the patent system exists, forget the grab you read here about patents on Slashdot.

Re:This was my companys idea in 2001

[pmadden]

Of course, this was also Thinking Machines idea a bit earlier. http://en.wikipedia.org/wiki/Thinking_Machines
It's good to see that MIT has perfected the technology.

• Build a machine with lots of processors.
• Get investors to buy into the hair-brained scheme.
• ??? (Mention that programming is a problem to be solved shortly.)
• Skip town with the cash (Profit!).

Hmmm. I think I'm missing something about a beowulf cluster, or maybe underpants.
It's scary how little history people know. Programming for multi-processor machines was part of the ACM recommended university curriculum back in 1968. Dozens of companies were going to revolutionize the world with parallel (anyone remember the Atari ATW? http://www.atarimuseum.com/computers/16bits/transp uter.html). If parallel worked, it would be really great; I'd like a big rock candy mountain and free energy, while we're at it. Amdahl's law http://en.wikipedia.org/wiki/Gene_Amdahl is from 1967 (this is the 40th anniversary, people!). Madness, sheer madness.

Re:This was my companys idea in 2001

[John Sokol]

Parallel processors on a single die (chip) is very different from Thinking Machines & beowulf clusters.

Up till now there were only 2 types of Parallel processing.

1.) loosely coupled. Thinking Machines & beowulf clusters for example are using this, these are interconnected with Ethernet or some other Network medium and send messages back and forth.

2.) Tightly coupled, this is SMP, NUMA, SNOOPY, basically shared memory system where each processor shares the same global memory space.

Each requires very different programming strategies and are limited to certain types of problems.

There is also a third form that is lesser know. This systolic arrays. An example of this is TimeLogic, and many DOD type projects.
This is usually done with a bunch of FPGA's and the math computations are done as a series of hardware pipelines without any CPU.

With the parallel core processor it's possible to make it like an SMP (share memory) type system, but you really get hammer with the memory bottleneck so after about 4 CPU's you don't really gain much.

What I had proposed with doing systolic array type of processing but with Simple but fast CPU's on one chip.
They would be connected with CPU registers that would pass data directly from one CPU to the next.
It's design would allow super tight coupling between each processor, so a programming problem wouldn't need to process a buffer at a time but could tackle problems that can't normally be broken up into parallel operations. For example a bignum math operation like multiplying 2 number that are 1024 bits long. Or large FFT, fast DVT, or matrix operations where each cpu could process part of a single operation that must be done serially, and can not be done using traditional parallel processing.

Specifically my interest was in video compression and image processing in real time. This is where DCT, motion vector searches Huffman coding and other operations that don't parallelize well would really get a boost using this type of processor.

Let the geeks solve the problem

[rbanffy]

"'What will make or break Tilera is not how many peak theoretical operations per second it's capable of (Tilera claims 192 billion 32-bit ops/sec), nor how energy-efficient its mesh network is, but how easy it is for programmers to extract performance from the device. That's the critical piece of TILE64's launch story that's missing right now"

Build a USD1000 desktop workstation, port Debian Linux to run on it and let the geeks out there adopt it.

There is no better way to explore a device's capabilities than to let the market do it.

I want one for myself. I am tired of the x86 architecture.

Re:ummm... Isn't Sun's T2 running 256 threads?

[Slashcrap]

The T1 was already doing 32, and the new T2 is supporting 256 in a single chip. Just wondering why "TILE64 has indeed brought us into the era of 64 general-purpose, mesh-networked processor cores on a single chip, and that's a major milestone", when the mile marker is already at 256?

Because this has 64 cores as opposed to 8 cores on either the T1 or T2?

Because the total number of threads supported by an 8 core T2 is 64 and not 256 as you wrote above?

Not 64..

[Namlak]

Actually, 42 cores is the answer.

Deep packet inspection

[Slavidian]

Tilera will succeed because the packet pushers want to be able to do deep packet inspection. Pay close attention to the first three in the apps list from their website:

Unified Threat Management
Network Security Appliances
In-line L4-7 deep packet inspection
Network Monitoring
Digital Video:
Video Conferencing
Video-on-Demand (VoD) Servers
Video surveillance
Media 'Head-End' services

The engineers in charge of this company should be ashamed of themselves. They are creating exactly the type of product that will help the telcos destroy the internet. DPI and UTM are completely at odds with the intentions of networking protocols. Tilera is handing over control of everything that you and I do online to the telcos. Where is Google? They should be diametrically opposed to the success of this company. Buy them up and quash them.

I for one

[tttonyyy]

I, for one, parallel welcome our new beowulf joke superseding overlords.
I, for one, parallel welcome our new beowulf joke superseding overlords.
I, for one, parallel welcome our new beowulf joke superseding overlords.
I, for one, parallel welcome our new beowulf joke superseding overlords. ... ... ...
I, for one, parallel welcome our new beowulf joke superseding overlords.

Re:I for one

[fava]

Actually that is a serial welcome, a parallel welcome (8 core) would be:
IIIIIIII,,,,,,,, ffffffffoooooooorrrrrrrr oooooooonnnnnnnneeeeeeee,,,,,,,, etc.

fava

Re:This All Fine and Good, But

[dm0527]

The same old tired, boring grind and stupid, inane and childish behavior by your fellow gamers?