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AMD Announces Triple-Core Phenom Processors
MojoKid writes "AMD has officially announced their triple-core Phenom multi-core processor offering, suggesting a triple-threat of processors, from dual-cores to triple-cores and native quad-cores coming to market this year. While the term symmetric multi-processing (or SMP) suggests a balanced approach of multiple cores in an even number of engines working together on a single workload, AMD offers that an odd number of processors can slice at that workload just as efficiently. Time will tell how this architecture will scale amongst various multi-threaded applications and real-world usage models. AMD is definitely moving to make use of these quad-cores that don't quite make the cut by testing them fully as triple-cores and realizing some revenue, rather than throwing them away."
Damnit, I haven't even used up all the cartridges that came with my Intel Core Duo!
I'm holding out for a processor that goes to 11.
Why Yes. Yes it does. From HERE: Inside, the Xbox 360 uses the triple-core IBM designed Xenon as its CPU. While graphics processing is handled by the ATI Xenos which has 10 MB of embedded eDRAM, its main memory pool is 512 MB in size.
There is no "I disagree" mod for a reason. Flamebait, Troll, and Overrated are not substitutes.
SMP doesn't suggest the number of cores should be a power of two, it doesn't even suggest "even number of cores".
It's about multiple cores processing simultaneously. Check the article I link to, even the damn example diagram has 3 cpu-s.
Wouldn't it make sense to sell any part that had at least one working core? Meaning that if in making quad-core chips, W% of them ended up only having one working core, X% had 2, Y% had 3, and Z% had four, wouldn't it make the most sense to sell all of these chips?
This implies that they have a way to use all four cores independently. Maybe they can't; maybe one core is "special", like the "master" core that has to be working for anything to work. Also this implies that the cores can detect that their sibling(s) aren't working and switch to a mode in which the sibling is not used at all.
Also, a question - when a core doesn't function properly, is it somehow disabled completely so that it doesn't use any power? Or maybe a core that isn't being fed any instructions doesn't use any power anyway?
And why should ``symmetric'' imply even? It merely implies that all cores see memory with the same class of service. And, in reality, aren't most AMD multiprocessors cc-NUMA machines, not SMP?
For most workloads, if they are fairly multithreadable, 3 processors available will be just fine. I know of very few workloads that require an even number of processors, and even if it were the case that the task were split into an even number of threads, the OS should have no problem scheduling on a reduced number of processors.
Hey, doesn't the XBox 360 have a 3-core PPC in it?
-- Erich
Slashdot reader since 1997
Symmetric just means the processors are equivalent (they all do the same generic tasks)... As opposed to an asymmetric system where different processors are assigned different roles (one does interrupts, one does graphics, one does IO, etc)...
SMP refers to the fact that all the processors are identical and share the same memory (in contrast to NUMA designs like multi-chip Opteron systems). However, I've seen more and more people refering to cache coherent NUMA designs like multi-core opteron and the upcoming CSI based intel systems as SMP systems which, while a stretch of the definition, is at least reasonable.
Suggesting that SMP has anything to do with having an even number of processors is just DUMB. It may be the case that SMP systems usually have an even number of cores (I don't know) but that's not what the writeup or article seem to be saying.
If you liked this thought maybe you would find my blog nice too:
Quite good, perhaps, but for less money you can certainly get better performance out of Intel. As much as I have loved AMD for the last decade, Intel is completely eating their lunch at the moment and Phenom and Barcelona are not going to save them. We can only hope that in the next couple of years, they have something in the pipeline that rescues them and their less than 15% market share, before someone gobbles them up.
I always thought that too, but the Xbox 360 has a 3 core CPU as well.
Supposedly 3 core is actually pretty nice in some ways, as each core has a direct link to the other two. On a quad core system, each core is linked to two others, so sometimes it takes two hops to get messages from one core to other, slowing things down.
There are a few possibilities:
1. The core is there and locked off via microcode like the extra quads on a cut-down GPU (e.g. Radeon x1900GT vs. x1900XT) and can be enabled with a microcode flash.
2. The core is there but the fuses that connect it electrically to the rest of the die are blown, so it is there but not able to be enabled.
3. The core was never there as the die only has three cores in it in the first place- you have a fully-functional piece of silicon, so there is nothing extra to enable.
Either way, it's really long odds you'll get a free core enabled. Nobody has been able to even upward-unlock the K8's multiplier and I know for a fact that is set in microcode (some guys on ExtremeSystems got a JTAG and found that out but not how to change it.) They will probably use the same method they used to disable one core on a dual-core die and sell single-core Manchester and Toledo-die chips and AFAIK nobody has unlocked any of those. I bet they have a few of the X3s be X4s with a bad die, but the X4 is a darn big chip at nearly 300 mm^2 and the cost reduction by using a native 3-core die would be mighty attractive to them so I guess that most will be #3 then.
Just "gittin-r-done," day after day.
Intel makes the Core 2 Quads by putting two Core 2 Duos together under the heat spreader. They are separate dies- go buy a Q6600 and pop the IHS off and look at the two separate dies yourself if you need proof. Intel tests the dies before they are mounted on the substrate, so a die with a bad core never makes it into the C2Q. Another fully-functional die is used in its place. The die with one bad core is either sold as a Celeron 4x0 or thrown away as defective. Intel doesn't make a single die with four cores like AMD is doing. Once they do, then they will have to worry about what to do with a quad-core die with one bad core. They can either pitch it, sell it as a 3-core, or disable another core and sell it as a dual.
Just "gittin-r-done," day after day.
This reminds me of the joke about the 3 dollar bill. Counterfeiters mistakenly make a 12 dollar bill, so they go to a rural state, like Idaho, to try to pass it off. Going into a store they ask for change. The clerk asks "would you like four three's, or two six's?"
Best regards.
Would someone tell me how this happened? Intel was the fucking vanguard of computing in this country. The Core Duo was the processor to own. Then the other guy came out with a three-core processor. Were we scared? Hell, no. Because we hit back with a little thing called the Core Trio. That's three cores and an fan. For cooling.
But you know what happened next? Shut up, I'm telling you what happened -- the bastards went to four cores. Now we're standing around with our cocks in our hands, selling three cores and a fan. Cooling or no, suddenly we're the chumps.
Well, fuck it. We're going to five cores.
For about $60, I can get a dual-core 64-bit processor at something like 2 ghz. Maybe I wasn't looking in the right place, but the cheapest Core 2 Duo I saw was over $100.
Also, you're absolutely right that we should hope AMD doesn't get gobbled up. The current Intel stuff, it seems to me, is a direct result of AMD dominating the price/performance ratios for so long, and even, recently, doing well with performance/watt. So even if you don't end up buying AMD, having them as a constant threat means Intel will be forced to compete.
Don't thank God, thank a doctor!
Quite possibly the best post ever.
"Who is the Journal of Quantum Physics going to believe?" --Stephen Hawking
Firstly, for any general multi-node graph, it's entirely possible for three, four, eight, or any number of nodes to be only one hop away from each other. See fully-connected mesh. For the four-node case, imagine a 2D square, connected on the four sides, plus two links connecting the "diagonals" of the square. In that topology, each of the four nodes are only one hop away from each other. Of course, as the number of nodes increases, the cost of fully connecting them increases, as does the processing cost to multiplex and process transactions into the node from the (n-1) incoming links, but with only four nodes it's entirely possible to create a fully-connected network.
Wiith AMD multi-core processors, all of the cores communicate using a fully-connected crossbar switch in the on-die northbridge - meaning all cores on the die are one "hop" away from each other, including the four-core case. What you're probably thinking of is a multi-socket system that only has two coherent links per socket - that would prevent you from making a fully-connected coherent interconnect for a 4-socket system.
It's actually kinda sad for AMD. In other markets they'd be making money.
After all their stuff:
1) Actually works (and is reliable compared to other computer stuff - RAM, HDD, motherboards, etc)
2) Is cheap
3) Is available in sufficient quantities
4) Performs ok
Only prob is Intel is now significantly ahead of them in many areas.
That's what you get for being in a high tech commodity market where lots of buyers actually go by specs and price and not by covenience or brandname.
If AMD was number two in the orange juice, soda pop or cooking oil market with just 15% share they'd still be making money. And they could sell the same standard juice/soda/oil for years without investing billions in fabs and processes.
AMD has lots of smart people working for them.
It's better to be number 9 in good industry than number 2 in a crappy industry.
Kids, learn from this. That's why smart parents discourage you from trying to earn a living as a movie star or singer, the number #10000 star/singer in the world doesn't make as much as the number #10000 lawyer/doctor.
You can do 4 objects and connect them all without oven using another layer. Picture a triangle with the other component in the middle. Connect every vertex to the middle. Make the traces to the middle zigzag a bit to even out the trace lengths, and boom, fully connected without any intersections. Not saying this is how things are done, mind you, but it is a silly argument to say three cores are good because they can be connected trivially. 3-core cpus are all about yield. Being able to sell components that had a flaw in a core, without reverting all the way down to a two core part (and by extension the two core price point), is important.
All that said, SMP has nothing to do with an even number of processors/cores. It just means each processing element of a system is roughly equivalent. So you have a choice of three parts to schedule something on, the scheduler can know all three are equally capable and the heuristics for processor selection are straightforward. ASMP typically has specific roles for each part (i.e. a dedicated processor for interrupts, etc etc)
XML is like violence. If it doesn't solve the problem, use more.
Another reason why powers of two are popular with multicore chips is that powers of two can be laid out into rectangles. If your multicore design is basically a copy-and-paste job with a little glue logic, it's a lot easier to lay out the cores. With something like the Cell, 8 is a nice number of cores since it allows you to have two rows of four. Three is just awkward.
The Cells found in the Playstation 3, however, did not have 8 SPU cores, they had 7. This is because most of the die space is the SPUs and you can dramatically increase yields if you only expect 7 of the 8 to work. If a single SPU has a manufacturing flaw, you just disable that one and sell pop the chip in a PS3. If none of them do, you sell it for more expensive blades.
AMD and Intel have been doing this for a while. Chips with flaws in the cache have some of the cache disabled and are sold more cheaply. In addition AMD chips are designed with three hypertransport controllers. If only one works, the chips are sold as Athlon 64s. If two work, they are cheap Opterons, if all three work, they are expensive Opterons (exactly how expensive depends on how many flaws there are in the cache area). Similarly, with the dual core lines flaws in one core result in them being marked down as single-core chips.
Intel, currently, sell quad core chips containing two separate dies. If either die has a flaw, it is sold as a Core Solo and not put in a dual-die package. AMD, however, are going to be making single-die quad-core chips. Selling three-core versions allows them to make use of the ones with a flaw in one core. This should help keep their yields high (and thus their costs relatively low), since it means that they can sell flawed chips almost irrespective of where the flaw is, just marking it down as a cheaper part.
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Before you call me incorrect, please take 2 minutes to look at some lecture notes from an intro VLSI course:
http://www.cse.sc.edu/~jimdavis/Courses/2005-Fall%20CSCE%20613/CSCE613-Week10-Chapter-04-05.pdf
You can clearly see on page 3 (slide 6) that metal1 and metal3 are directly on top of each other. As I stated in a different post, you're confusing metal layer/wire routing in an IC with entire logic devices (transistors/gates/flops). Let me repeat it again for you: metal layers in an IC can cross.