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Low Voltage Is Key To Energy-Efficient Chip
An anonymous reader writes in with news from the International Solid State Circuits Conference in San Francisco of a new energy-efficient chip designed by researchers at MIT. It's said to be able to run on 1/10 the power of current chips. Texas Instruments worked with MIT on the design, which is maybe five years from production. "The key to the chip's improved energy efficiency lies in making it work at a reduced voltage level, according to... a member of the chip design project team. Most of the mobile processors today operate at about 1 volt. The requirement for MIT's new design, however, drops to 0.3 volts."
In Germanium the voltage is 0.3, if I remember correctly. So it depends on the materials used.
In this case, they're operating the transistors in a sub-threshold voltage environment. A full channel never opens for the transistor, but energy will trickle through at different rates.
Instead of the typical "open/closed water pipe valve" model of the transistor, imagine having a leaky bucket, and then determining 1 vs 0 on how many drops get through.
It's a tough area to design circuits in because of the very delicate balance. It doesn't take many electrons (or much process variation) to bust up your circuit.
I just finished reading the article, and it's actually got some exciting stuff. Having the processor scale its voltage when it's idle is a great idea. Current processors will change their FSB multiplier when idle so that they run at lower clocks and consume less energy, but a computer chip that could call on less voltage in a desktop machine, as well as lowering its number of clock cycles would be a huge energy saver. Though I do find the summary misleading. This processor will not run on 0.3v unless it is idle. Once you put a load on it, you have to increase the voltage.
Less transistors switching is only part of the story.
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Maybe a more signficant factor in determining the power consumption of a CPU is the technology process choice.
Intel typically tune their process for performance, at the expense of leakage. This lets them squeeze out a couple of GHz in terms of clock speed, but it means that the power consumed when the chip is doing nothing at all (i.e. idling) is much larger. The CPUs that are put into cell phones (from companies like ST, TI, Broadcom, etc, etc) are normally fabbed with a "low power" or LP option. This reduces the maximum speed that you can get out of the processor, but reduces the leakage problem significantly. If the cell phone is only using the processor 1% of the time (think of how long it spends powered on in your pocket), then there is no point in having the best 3D games on your phone, if the stand-by time is 15 minutes.
Switching between these standard (or GP) processes and LP processes is not quiet straight forward, as you need to design all your mixed-signal / analog blocks (think PLLs, bandgaps, regulators, etc) for both nodes. While I'm sure Intel could probably afford to do this, they would then have to turn around and support this process in their fabs, which would eat up their resources for their processor market.
If you compare the numbers: Intel can sell their processors for hundreds of dollars. Phone manufacturers buy processors from the other Semicos at about 10-15 dollars each. Guess where the better margin is
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Most current desktop chips do scale their voltage (such as the Core 2 Duo). The drop isn't all that dramatic, it drops from approximately 1.3V to 1.0V. But it does drop.
Power consumption in a digital circuit can be approximated by the formula:
Pavg = N*f*C*Vdd^2 + Pleak
where N is the probability of a gate switching during one clock cycle, f is the clock frequency, C is the average gate capacitance, Vdd is the supply voltage, and Pleak is the power loss due to current leakage. Since power is proportional to the square of the voltage but directly proportional to everything else, reducing the voltage has a much greater impact on total power consumption. Going from 1V to 0.3V implies a >10x dynamic power reduction.
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Your current multigigahertz processor relies on dynamic logic. Dynamic logic does not work at subthreshold (roughly below 1V). This chip almost certainly uses static logic and will not be as fast as a modern CPU no matter what the voltage.
:P
Gigahertz speeds are not impossible for static logic, in fact most modern processors are in their vast majority (and perhaps entirety, though I couldn't prove it) static logic, and perform quite a bit of logic in a single clock using static circuits. 45nm transistors are really fast, they don't necessarily need the tricks (and design complexity, and manufacturing risk) of dynamic logic to get to high speeds. Maybe the double-clocked ALUs in the Intel P4 series used it for example, but otherwise static logic rules the day.
Certainly you're right that it's unlikely that this chip would clock that high regardless of voltage. Static logic likes super-threshold voltages too.
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TFA isn't very techincal, and makes it sound like the MIT team isn't doing anything very interesting (they mention 8-transistor SRAM cells, but even regular CPUs sometimes have to use them). The interesting story here is that the chip is being operated at a voltage below the voltage where the transistors are normally viewed as being "on". In this region, transistors operate more like amplifiers than digital switches.
One cool thing about this is that the leakage power will be negligible. Leakage currents are generally exponential with respect to voltage.
Another cool thing is that the chip can actually operate at the low voltage. It's not too hard to make a chip retain state at very low voltages, but as soon as you want to do anything you usually have to raise the voltage back up before execution resumes. Any task that requires a small amount of work frequently will benefit from something like this. A contrived example of where this make a big difference is in a poorly-architected MP3 player in which the CPU has to shuffle a few thousand bytes per second to a sound chip, but in very small chunks (this poorly-architected sound chip has a very tiny buffer), hundreds of times per second. A normal chip would be constantly jumping to a high voltage and going back to sleep; depending on how long the voltage transition takes, it might have to stay in a higher voltage state constantly. This chip, on the other hand, could operate continuously at the "sleeping" voltage.
The catch is that transistors operating in the subthreshold regime are going to be pretty slow, so for any tasks that require high performance you'll have to bump the voltage back to a more normal range.
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Power = Current * Voltage
To reduce power consumption, you either have to reduce the voltage or the current.
While your formula is right, it's not too applicable for chip power usage because current is not a constant. The formula you will normally see is
P = P-switching + P-leakage
Now, P-switching = fCV^2, so you can reduce it by reducing the clock frequency, voltage, or the number of transistors. But, P-leakage actually increases exponentially as the gate threshold voltage is reduced -- so, reducing the voltage too much will not help, either. There's only so far you can go before leakage power becomes the dominant one and reducing voltage further doesn't help.
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Dear God, how did this get modded Informative? The parent is confusing CMOS logic with NMOS logic (you do NOT use static loads with CMOS logic), and FETs do not have a parameter called "activation voltage".
For a description of CMOS logic that's actually accurate, check out the wikipedia article here:
http://en.wikipedia.org/wiki/Cmos