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Cell Hits 45nm, PS3 Price Drop Likely to Follow
Septimus writes "At this weeks ISSCC, IBM announced that the Cell CPU used in the PlayStation 3 will soon make the transition to IBM's next-gen 45nm high-k process. 'The 45nm Cell will use about 40 percent less power than its 65nm predecessor, and its die area will be reduced by 34 percent. The greatly reduced power budget will cut down on the amount of active cooling required by the console, which in turn will make it cheaper to produce and more reliable (this means fewer warrantied returns). Also affecting Sony's per-unit cost is the reduction in overall die size. A smaller die means a smaller, cheaper package; it also means that yields will be better and that each chip will cost less overall.'"
I don't know what it is about measuring things in nanometers and terabytes that gives me such a hardon.
Thank you IBM.
PS: Please don't put Skynet online.
Virginia is for lovers. EVE is for griefers.
My only question is, will this reduce the cost?
This would be a great thing if they allow PS3/Linux users to access 7 of 8 SPUs instead of only six.
Otherwise, it's nice but not that big a deal...
This fits in well with the rumors of a slim version of the PS3 in the works. See here for more details.
Curiosity was framed, Ignorance killed the cat.
A price drop would be nice (though the PS3 is now competitive), but the more interesting bit is when is the PS3 slim going to appear. All the pieces are in place for a slim. Sony have been aggressively shrinking the motherboard in the PS3, and the chip size has dropped from 90nm, to 65nm and now 45nm. All that means less power (smaller PSU) and less heat (less fans & heatsinks). There have been other announcements such as thinner blu ray reader headers. It can only be a matter of time before a slim and I think it will hit before the holidays this year. I think it will sell by the shitload too when it does appear. The question is will we see a slim 360 to compete with it? I think there must be a lot of empty space in the 360 too.
The article mentions the cost savings to Sony (maybe they'll be passed on to the consumer...two or three years from now), but the real kicker is at the bottom where IBM apparently had to maintain cycle compatibility with the old chip to make sure they don't break any games. They didn't use the die shrink to optimize or enhance any parts of the chip like you normally would. The supercomputer folks might end up losing out a bit in an effort to keep the game console folks happy.
I read the internet for the articles.
It would be really great that they are moving to a smaller process, (/me takes deep breath)
IF THEY WOULD SELL YOU THE DAMN THINGS!
Where I work, we approached them to try to buy Cell processors for our equipment: the SPUs would make dandy DSP replacements, and we really could use the closer coupling of the processors instead of having a bunch of DSPs and spending all our time schlepping data around.
IBM wouldn't sell us any modules, wouldn't let us design our own CPU board, nothing. They seem supremely uninterested in actually getting these out into the hands of anybody other than their own divisions and Sony.
HEY IBM! How about you guys release these in a MicroTCA formfactor, or as a module that can be integrated into a MicroTCA?
www.eFax.com are spammers
Is the fact they've dropped hardware PS2 emulation.
[Fuck Beta]
o0t!
Since when does going to a smaller process increase yields?
Always has.
Assume there will be 20 defects on a wafer that will render 19 large chips (out of 100) unusable. Your yield is 81%.
Same 20 defects, but affecting 20 small chips (out of 170). Now your yield is 88%, or 150 chips versus 81 chips per wafer.
The number of defect sites per wafer is generally rather constant, thus the more chips you can fit on a wafer, the better the yield.
If' they're dropping cooling components due to lower heat output, I wonder if that means this picture is for real.
Moore's law is dead. Atoms aren't getting any smaller. With 5 atoms thick, when you try and go to 2.5 atoms thick, let me know and I'll get far away.
The reason is that wafer size doesn't change. I don't remember what is current, 8 inch I believe (that's the largest I've seen) but regardless. So when you reduce the size of an individual chip, you get more chips per wafer. Now unless the percentage of chips that fail increases, that means you get a better yield/wafer.
Well cost is based per wafer. It doesn't cost any more to make a wafer with 1000 small chips than it does to make one with 4 big chips. In either case it is the same size wafer, same mask, same process, etc.
Now yield could go down if a company has problems with a new process. Suppose that the old process yields 10% non-working chips per wafer. You get a new process that yields 20% more chips per wafer than the old one, however now 50% of them are non-working. That would equal a lower yield, despite the more chips per wafer.
However assuming a roughly equal failure rate, shrinking the die size will increase the yield.
The size of a defect is of a fixed size. Usually it is a particle of dust that got in the way of the optical etching process. The distribution of such defects is even across the surface of the silicon wafer, so the distribution can be modelled mathematically.
Suppose there are 20 defects across the wafer. If your chip were the size of the entire wafer, it would be guaranteed to be defective.
Try half the size of the wafer, and there would be on average 10 defects. A quarter of the wafer, 5 defects. If you have a chip that is one hundredth the size of a single wafer, then the odds are now in your favour; on average 20/100 that you will have a defect, 80/100 that you will not.
The Cell processor is etched with eight processors anyway. If one is defective, they can ignore it, otherwise if all eight are working, then they will just deactivate one.
I wonder how long it will be before they start adding more processors to the chip.
Vintage computer adverts: http://www.vintageadbrowser.com/computers-and-software-ads
Relevance of CBE beyond PS3 of course depends in large degree on its computing performance. For the applications I've looked at, I haven't been very impressed. They say it does 204GFLOPS, but approaching that requires being able to use all multiply-add instructions, which count as two operations. (Some sources say the two operations per clock cycle per SPU is due to there being two pipelines, however, only one of the pipelines handles arithmentic operations and the other is exclusively for load, store, control, and a few shift operations.) Also, it seems to take a lot of select, shift, and shuffle instructions to make efficient use of the quadword (SIMD) instructions. With Xeon and Opteron, use of the quadword instructions seems to require far fewer other additional cycles. And this is with floats, with instruction related stalls completely eliminated on CBE through careful loop unrolling and other methods. (The quadword instructions have 6 cycle latencies.) I can only get performance comparable to 2 quad-core Xeons, which doesn't seem that good considering what is advertized, and considering the 4x difference in the peak performance specs. And CBE does much worse where double precision is necessary, with 6 cycle stalls being unaviodable on every instruction. It seems overblown. Comments?
Defectivity (i.e. the "dust problem") is just one of the yield detractors. There are many more and they get worse and worse. For instance, there are litho problems, etching problems, CMP problems, not to mention gate leakage, and a bunch of other parametric issues. So, you can not just look at defectivity. Even if you did, with a smaller feature size, small particles that could be tolerated in an older generation will now cause yield loss.
PS: the distribution you are talking about is a poisson distribution