Intel Patents On-Chip Cosmic Ray Detectors

holy_calamity writes "Intel has been awarded a patent for building cosmic ray detectors into chips, to guard against soft errors where a high energy particle from space changes a value in a circuit. It's a problem that largely only affects RAM. As component sizes shrink futher, "this problem is projected to become a major limiter of computer reliability in the next decade", says the patent. Intel's solution is to build in a detector that responds to cosmic errors by repeating the latest operation, reloading previous instructions, or rolling back to a previous state. You can also read the full patent."

Comments

How?

[mistersooreams]

How did they manage to build a detector that can work out whether the cosmic rays collided with the actual bits (no pun intended) that hold the data? According to the oracle, cosmic rays collide with nuclei in an essential random way, so there's no way a detector could just see a ray passing through and know whether it was on a collision course. Perhaps they are detecting the pions and other subatomic particles that result from a collision actually occurring? If they've found a way to do that then it sounds fairly ingenious to me and a well-deserved patent.

Re:How?

[hedwards]

They didn't, they've created a detector which works out whether the chip was hit by a cosmic ray or not. Then the ram is somehow restored to the state previous to the last operation and that operation is then repeated. I'm not even sure that hit is the right word, they've developed a detector that is capable of knowing when a cosmic ray travels through the same space as the chip, I don't know that they care whether or not the ray actually hit something or just traveled through the open space between the atoms.

It's a lot less likely to cause problems than trying to guess which bit it was, and far less expensive than building a RAIMM(TM) to compensate for it.

Re:How?

[Waffle Iron]

but if you can interact with it then it's not a problem, because once it interacts with something then it's gone.

With cosmic rays, it's not just "gone". Instead, you get a shower of new energetic particles generated by the collision which compounds the risk of operational errors. The patent specifically mentions alpha particles knocked out of the atoms in the chip by the ray which travel through the circuits causing havoc.

The patent also mentions that the detector may sense side effects of collision (such as voltage spikes) rather than the ray particle itself. Thus, the damage has already been done by the time the detector sees the event.

ECC Memory not good enough?

[beefsprocket]

Cosmic ray detector certainly makes for better marketing hype than ECC.

Just fantastic

[elrous0]

I know at least four people who REALLY could have used this. Oh well, too late now.

Shouldn't take long...

[canada_dry]

It won't take long for someone to figure out how to detect the gamma errors and create what amounts to a geiger counters on laptop computers. If this bill passes http://www.villagevoice.com/news/0803,thompson,78873,2.html will everyone be required to get a permit for their laptop computers? ;-)

Re:Mainframes allegedly already do this

[Ceriel Nosforit]

I saw a display in the visitors' center at CERN that detected cosmic rays. A cloud chamber, maybe.

Either way, the... 2m by 2m (IIRC) display would detect cosmic rays about once every 2 seconds. This would mean my PC case is perforated by cosmic rays several times each minute. That's not rare.

Current work and contribution of this paper

[quo_vadis]

Currently, chips (both computational and memory) are protected against soft errors using multiple methods. There are rad hardening methods (both hardware and software) and most of the latest research involves using error correcting codes. Simply duplicating the output and comparing can only detect errors in one bit. The more the times you duplicate, the more you can detect (it progresses as n-1), and the max length of error that can be corrected is half that. However, this takes a lot of space (duplication that is), so generally other codes such as Hamming or BCH codes are used.

The main problem using codes and everything is that cosmic ray errors cause whats called single event upsets and most codes can not detect 100% of errors where the hamming weight of the error (sum of number of ones in the error vector) is larger than the designed specification of the error. The problem comes when the SEU manifests itself as a multi-bit fault and the error vector cannot be detected by the code. SEU's are the most common type of errors in space application : See http://www.eas.asu.edu/~holbert/eee460/see.html

The contribution of the cosmic error detector is that if you know you have a cosmic ray at some point in time, you can flush and redo your computation (for computation channels eg microprocessors etc) or flush that line in memory (for memory channels) in case of SEU's and that is a pretty big deal.

Re:Current work and contribution of this paper

[museumpeace]

you mention rad hardening...some of that tech. would have been first needed in military satellites and so not necessarily divulged in a patent. One kind of rad hardened circuit that used to be prohibitive but with advances in solid state fab requires a particular kind of redundancy. It has been described in prior literature kinda like this: build a functional duplicate of each storage or processing element in a parallel layer so that ...

• each element is aligned right over its corresponding element in the 2nd layer.
• bias the logic of one layer such that the burst of conduction band electrons that would accompany a gamma ray hit will report a false "1" if anything.
• bias the corresponding logic in the other layer so that that same burst of electrons...which will befall it at exactly the same time an place as its aligned circuit...will fault to a "0",if anything
• gate the primary layer's output by the !XOR of the two layers: whatever the state of the circuit was supposed to be, it will be disabled until the transient from the gamma ray has been quenched

Processor instruction retry

[br1an.warner]

POWER6 has actually be shipping with this for a while - if an instruction fails (cosmic ray or not, although in terms of random bit-flipping events they account for a large percentage), it gets automatically retried, transparently to the rest of the system. Without this sort of thing you generally take a hard fault - so this type of protection is great to see. Same thing on a SPARC64, incidentally (but not UltraSPARC - ie Niagara or children). What sets the POWER6 apart from both SPARC64 and this patent is if that instruction fails repeatedly Possibly indicating a chip fault), in many cases it can actually back the instruction out of the failing core and slap it onto another core, also transparently and avoiding a hard crash. Someone noted that this has been done on mainframes for years - yup, also true. This is another case of UNIX-class technology making inroads up the platform stack.

If the problem is with RAM...

[sbaker]

For RAM - there is really no problem - just use error checking. It's got to be easier to add an extra couple of bits to the width of your RAM to permit error-correction than to have a cosmic ray detector for every single bit.

The tricky problem isn't RAM - it's computational elements. There is no single way to error-correct computational elements because they are so diverse. A multiplier would need different protection to an adder which is different from a shift-register. Hence, the idea of rolling back (say) the last instruction executed and having a "do-over".

But for large arrays of homogeneous circuitry - like RAM - this doesn't seem worth the effort.

Re:If the problem is with RAM...

[saltydog56]

You are exactly right that the real problem is not the functionality of the memory chips, but rather the processor chips. For a number of reasons (but having said that it is very likely that a significant portion of the the problem of soft CPU chips is the on chip level one cache)

On a regular basis I participate in the "radiation testing" of laptops intended for use on both the Space Shuttle and the International Space Station. This testing is normally done at Indiana University's Cyclotron Facility in Bloomington, Indiana. This past fall we completed testing on a group of laptops which implemented Intel's dual core Centrino Pro processors. Testing is conducted by hitting each of the components in the laptop with a proton beam while monitoring for induced errors.

While the results of the testing varied by memory manufacturer, by far the softest component in the laptop was the CPU itself. That said, these processors actually did fairly well compared to some of the previous generations of CPU chips we have tested over the years.

The rule that the smaller the die size, the greater the error rate does not seem to apply. For example, a number of years ago we tested a number of laptops using the Intel Pentium 3 mobile chip. Performance was so dismal that the decision was made not to procure any system based on that chip.

Later testing of laptops based on the Pentium 4 mobile chip showed a dramatic turnaround - the Pentium 4 mobile chip, with its smaller die size actually out performed both the pentium3 mobile and the Pentium 2 chips then used for on-orbit operations. Our group does not do any analysis of "why" a failure occurred, only the collection of data to assist in the selection of suitable devices for use on the Shuttle and the ISS.

The bottom line - die size is only one of the factors which come into play in determining how a chip will perform when hit by ionizing radiation. (one of my favorite theories is the declining deltas between a 1 and a 0 - in days gone by it could have been as much a five volts but is commonly down to around 1 volt in todays modern processors - this could serve to bring any electrical disruption caused by a particle strike closer to the threshold of changing a one to a zero - but what do I know, I am just a software guy)

The concept of building a detector into chips is interesting, but not enough detail is provided to make a judgment on its feasibility. Single Event Upsets (SEUs or Bit-flips) are caused when a sub atomic particle such as a proton or a heavy ion slams into the silicon causing either an electrical disruption or damage to the silicon itself.

The key here is that these particles are so tiny compared to the circuit itself that, from my perspective, unless the "detector" somehow encapsulates the whole circuit it is unlikely even notice the passage of a proton or other particle. To make detection even more difficult you must remember that you are working in a three dimensional environment - you can not predict the direction of travel, its energy level, or the location of a "strike"

However, dealing with the effects of radiation on electronic components is something we are going to have to learn to deal with someday, so this research is both exciting and worthwhile.

Why don't they...

[sokoban]

... Just mount the chips in a vertical fashion. I work in an X-ray crystallography lab and we have a large format CCD detector. It's maybe about half a foot in diameter, but because it is mounted vertically, I see a cosmic ray streak maybe once every 200 or so 40 second exposures. Compare that to a cosmic ray detector of roughly the same size which is mounted horizontally in the other side of the building. It's counting cosmic rays almost constantly.

Re:Mainframes allegedly already do this

[SeekerDarksteel]

it seems painfully inefficient to 'redo' stuff that doesn't seem to be wrong just because a cosmic ray was detected.

1) The likelihood of a cosmic ray is ridiculously small. So small in fact that the cost of rewinding progress when they are detected would be completely unnoticeable.

2) We *do* have the ability to package CPUs such that they are protected by CPUs. The problem is that the packages are so large and expensive that no one would buy them given the current probability of soft errors.

So the solution is most definitely NOT to stop shrinking transistors. Even in 10 process technology generations, the mean time to a soft error actually affecting a bit on a CPU is something like 1 million hours. Never mind whether or not that particular soft error is critical.

Re:Mainframes allegedly already do this

[kesuki]

well, if the detector is the size of a penny, then yes probably pretty rare to detect cosmic rays... but if the detector is the size of a pc case, it will get hits every few seconds. cosmic rays ARE very common, and not all of them are magnetically deflected, or stopped by the atmosphere. they just happen to be very small, and the frequency of hits to a small target is less than to a large target. about 8% of the radiation humans are exposed to each year are from cosmic rays. http://en.wikipedia.org/wiki/Cosmic_ray

so clearly to a human sized target, the impact ratio is significant.

we used to detect 1 or 2 hits a week

[petes_PoV]

Just to quantify the effect, the Sun E10000 Starfires we used a few years ago had ECC error counters built into the operating system. When I asked what they were for the salesman told me straight that they detected/corrected cosmic ray hits.

More for laughs than anything else, I started logging them and found that a server with 16GB got maybe one ot two hits per week. After that I started to take ECC seriously - for professional quality servers.

You probably don't need it for the domestic appliance quality stuff that people run at home - but for real work, get some decent kit

I have a better solution.

[Xest]

Tin foil hats, for RAM!