Record Setting Silicon Resonator Reaches 4.51 GHz

bibekpaudel brings news that researchers from Cornell University have developed a very small silicon microresonator that vibrates at the highest frequency ever recorded for such a device: 4.51 GHz. Typical quartz-crystal oscillators, commonly used in electronics as clock signals, are about a millimeter wide and operate in the KHz - MHz range. The newly developed microresonator measures 8.5 micrometers long and 40 micrometers wide, making it ideal for use in smaller circuits and microprocessing. Quoting: "One of the advantages of silicon microresonators is that they can be integrated directly into microchips using conventional manufacturing techniques, making them cheaper to produce and easier to fabricate small. Also, multiple resonators of different frequencies could be put on the same chip, says Ville Kaajakari, an assistant professor of electrical engineering at Louisiana Tech University. In a cell phone, for example, high-frequency resonators could filter out interference from other sources of radio signals."

Comments

Zippy!

[ThePromenader]

Nice to see things speeding up : P

FIRST POST!!!!

[Oktober Sunset]

Or at least it would have been if I had one of those.

Re:FIRST POST!!!!

[Oktober Sunset]

Yea, I didn't read the summary at all. Got about as far as 'record setting'.

this will benefit lower freq apps too

[v1]

Something I'm surprised the article did not point out is its applications in lower frequency use. If you want to create a stable clock that counts seconds, you don't make an oscillator at 1hz (one beat per second), you create one that does much more, say 1000hz, and then divide that by 1000. So if you are off by a few cycles it doesn't matter much. The greater this multiplication the better. So a fairly stable 4.5ghz reference could be divided down to make an extremely accurate and stable say, 500mhz signal.

Re:this will benefit lower freq apps too

[The Living Fractal]

What about the overhead in dividing 4.5 billion so often?

Seems to me there must be some kind of sweet spot, not just 'more is better'.

Re:this will benefit lower freq apps too

[corsec67]

I don't think it would be diving by N on every cycle, but adding 1 to a counter, and when the counter equals N, you do one of the low-frequency cycle.

Re:this will benefit lower freq apps too

[The Living Fractal]

Checking if a counter == x, for ever increasingly larger values of x, will still cause increased overheard. Storing the numerical value of 4.5 billion, in binary, is 100001100001110001000110100000000 unsigned. So a 32bit register won't even hold it, if my evaluation is correct.

Whether or not the increased overhead is more detrimental than the increased accuracy is dependent on the application I suppose. But I guess all I meant to say is that 'more is better' is not always the case.

Re:this will benefit lower freq apps too

[Telvin_3d]

I'd imagine that this would not be something implemented in software but rather a dedicated system clock. The oscillator would be slaved to a tiny bit of dedicated circuitry that handles the count and all the outside system sees is the output number. It's a black box. From the point of view of the rest of the system, this would have no more overhead than a dedicated clock running at the lower frequency.

Re:this will benefit lower freq apps too

[Anonymous Coward]

Counters are exceptionally easy. These will be realized in actual hardware. Checking whether a counter is a number is really rather easy. As it reaches the count, you reset the counter. a 64 bit counter requires only about 32+16+8+4+2+1 = 64 two input gates to realized a pattern match for any number. This is about 256 transistors(can probably simplify it significantly. The counter itself only requires abo

Re:this will benefit lower freq apps too

[AdamHaun]

You don't do it with a CPU. You do it in hardware with a digital counter, like this:

http://www.play-hookey.com/digital/ripple_counter.html

Dividing by two is easy -- just take the output of one of the flip-flops. Dividing by other numbers can be done by connecting the flip-flop outputs and/or their complements to an AND gate. This requires some extra circuitry and wiring, but in an integrated circuit the overhead will be insignificant. Even in a discrete circuit, if you make the reference 2^32Hz (~4.2GHz), you're only looking at maybe two counter ICs to divide down to 1Hz, although no counter IC I know of can handle a 4GHz signal.

The real issue with using this would be whether your manufacturing process can make transistors fast enough for it. The quote in the summary suggests this will be popular in an analog role for high-frequency applications like wireless. Maybe we'll see discrete timing references too.

Re:this will benefit lower freq apps too

[Anonymous Coward]

with a relativly small construct you can divide a signal by a factor two in hardware -> 2^22.1015 is about 4.5 million so this should take lesss space than a quartz
and overhead is 0 because as mentioned, this is not part of the rest of the system!

Re:this will benefit lower freq apps too

[gringer]

Huh? You're checking a single counter to see if it overflows, nothing too taxing about that. The effort comes when the overflow happens, but it's really not much more effort
Here's the logic:
[0) Clear all counterincremented flags]
1) Increment counter(1) by 1 (mod some number like 256, 65536, etc)
2) if counter(1) = 0, it must have overflowed, so increment counter(2) by 1 (and set counterincremented(1) flag)
3) if counter(2) = 0, it must have overflowed, so increment counter(3) by 1 (and set counterincremented(2) flag) ...
n) if counter(n-1) = 0, it must have overflowed, so increment counter(n) by 1 (and set counterincremented(n) flag)

Of course there's a bit of trickery needed as you approach the target number:
Start:
0) Set step = n
After the increment loop:
1) if counter(step) has incremented,
2) if counter(step) is equal to target(step),
3a) if counter(step) > 0, decrement counter(step) by 1
3b) if counter(step) = 0, we've reached the target number

kcalc tells me that I'd need 5 bytes to store 4.5 billion, so you could have 5 1-byte counters (and have overflow happen more often), or 3 2-byte counters, and so on.

Re:this will benefit lower freq apps too

[gringer]

Damn proofreading...

3a) if counter(step) > 0, decrement counter(step) by 1 should be

3a) if counter(step) > 0, decrement step by 1

Re:this will benefit lower freq apps too

[Dachannien]

The counter itself only requires abo Poor guy must have run out of die space.

Re:this will benefit lower freq apps too

[The Living Fractal]

Yea, and I was going to say....

No but really, I see the light. Also your point about the IC used to do this at 4.5ghz is well taken.

Re:this will benefit lower freq apps too

[bdcrazy]

Few thousand transistors out of 1-2 billion now? I'm sure that th

Re:this will benefit lower freq apps too

[Gibbs-Duhem]

The only thing that matters is the accuracy. If your 4.5gHz clock is accurate to 1ppm, it will be off by 4500 counts every second, which happens to be equal to a drift of 1 millionth of a second every second. If your 1Hz clock is accurate to 1ppm, surprise, it will also drift by 1 millionth of a second every second.

Not to say you would use a 1Hz clock for a second counter, but this is more because it's convenient to not have to wait around in software for a clock edge to start calculations, and because the accuracy goes up when you get to real resonators (which don't exist so much at 1Hz).

Re:this will benefit lower freq apps too

[Original Replica]

Why is it necessary to count to 4.5 billion for a 500mhz clock? Every nine ticks of the 4.5ghz clock give one click to the 500mhz clock. Counting to nine is easy.

Re:this will benefit lower freq apps too

[kestasjk]

Clock dividers don't work by dividing numbers. You have a counter, and each time the clock changes the counter increases. If you wanted to divide a clock by, say, 8, you would use a simple 3 bit counter, which would only require 3 flip-flops and would cause absolutely no performance hit and a tiny amount of die space.

In-clock:0, Counter:000, Out-clock:0
In-clock:1, Counter:100, Out-clock:0
In-clock:0, Counter:010, Out-clock:0
In-clock:1, Counter:110, Out-clock:0
In-clock:0, Counter:001, Out-clock:1
In-clock:1, Counter:101, Out-clock:1
In-clock:0, Counter:011, Out-clock:1
In-clock:1, Counter:111, Out-clock:1

Definitely no need to do any division in a clock divider.

Re:this will benefit lower freq apps too

[Anonymous Coward]

The Intel p4 processors had alus that ran at twice the clock frequency. So the 3.8-4ghz cpus had actual circuits running at 7.6-8ghz and they were demonstrating 10ghz transistors a few years ago. Now the whole cpu wouldn't be running at this frequency, just the portion dealing with the oscillator.

Re:this will benefit lower freq apps too

[noidentity]

What about the overhead in dividing 4.5 billion so often?

What about it? If the goal is higher accuracy, having higher cost in the form of more silicon (a longer divider) is generally going to be expected.

Re:this will benefit lower freq apps too

[AdamHaun]

Yeah, I know Intel's CPUs can do it, but your average ASIC process is probably a different story...

Re:this will benefit lower freq apps too

[camperslo]

Something I'm surprised the article did not point out is its applications in lower frequency use. If you want to create a stable clock that counts seconds, you don't make an oscillator at 1hz (one beat per second), you create one that does much more, say 1000hz, and then divide that by 1000. So if you are off by a few cycles it doesn't matter much. The greater this multiplication the better. So a fairly stable 4.5ghz reference could be divided down to make an extremely accurate and stable say, 500mhz signal.

Wow, you're all over the spectrum mentioning 1 Hz and 4.5 GHz in the same discussion. They're really very different animals from a practical standpoint. Things like watches/clocks (in the traditional time keeping sense) generally use a pretty low frequencies as the reference. Since the simplest frequency division is using powers of 2 (chained flip-flops), something like 32.768 KHz is common. The lower you start, the less division you need. Also, with MOS/CMOS technologies where the bulk of the power consumption comes from charging/discharging gate capacitance during switching the power consumption is minimized by picking a low frequency.

Most things causing frequency errors tend to do so more as a percentage, so starting at a really high frequency and dividing down normally doesn't make things better. Resonators generally have to be physically larger for very low frequencies, so division is more common in that case.
A combination of dividing down and multiplying up is seen in things like frequency synthesizers. That's what one uses to digitally tune an oscillator in a receiver for getting a bunch of different channels. That beats having a crystal for every channel.

For signals needed at a very high frequency it is simpler to have an on-frequency resonator than to use a lower frequency one with a multiplier (phase-locked loop, filter tuned to harmonic, etc).

As for frequency accuracy and stability a higher frequency resonator isn't inherently better or worse. That depends on the accuracy of manufacturing tolerances, temperature coefficient of the materials used, sensitivity of the resonator to changes in circuit capacitance, and the stability of the circuit capacitance with variations in temperature and voltage.

There are already plenty of quartz crystal and other resonators for use below a few hundred megahertz. While oscillators for clocks/transmitters etc may be the first thing to come to mind, filters are also a major application. SAW (Surface Acoustic Wave) filter dramatically simplified channel-width filtering in television receivers, and ceramic filters simplified things like F.M. radios. Those go beyond simple resonators since they are actually bandpass filters with carefully tailored rejection characteristics for signals adjacent to the pass band.

Many receiver designs shift an incoming signal to a lower frequency by mixing it with an internally generated signal. But that type of superhetrodyne conversion can shift signals the same distance above AND below the oscillator frequency down to the lower frequency for processing. Which ever one is undesired is called the image frequency. To avoid interference from signals near the image frequency, filtering is needed ahead of the conversion. It sounds like the resonators developed might be a simple and cost effective way of providing that sort of filtering. Besides cell phones, 802.11b (2.4 GHz) and future retired NTSC U.H.F. television spectrum data communications are obvious major applications for this.

It'll be interesting to see how good of filters come from this technology. Beyond accuracy of the resonate frequency, getting desired pass/reject frequency response curve shape and low insertion loss are very important characteristics for filter applications.

Re:this will benefit lower freq apps too

[MindStalker]

A chip will generally have a constant drift. Say your 1Hz clock has a drift, you can fix the drift but previously you might have been a little more than a second after fixing it you were a little less than a second because the second actually landed down in the mid-point between the 1Hz. Its a problem of repeatable halfing the distance to the error, sure you'll never technically get there but at 4.5Ghz you can get much much closer.

Re:this will benefit lower freq apps too

[Anonymous Coward]

silicon mems resonators are - to date - no threat to quartz frequency devices except at *very* loose tolerance applications. A Q of 10,000 is a poor Q for a quartz resonator. At 4.5 GHz - it may be nice but not particularly attractive. Moreover, the TCE of silicon makes for poor frequency stability over temperature. - Lots of temperature compensation required. Oh and BTW - stability and accuracy DO NOT change with frequency. Fractional frequency offset - usually ppm (parts per million)- is the same at 1 Hz as it is at 1e9 Hz

Re:this will benefit lower freq apps too

[frieko]

A counter is child's play compared to a whole ALU. And most asic fabs are only 1 or 2 generations behind Intel.

Re:this will benefit lower freq apps too

[cheater512]

Its all done i hardware. There are no such problems.

Re:this will benefit lower freq apps too

[insignificant1]

That isn't how the process works. First, you can measure phase error (timing error) or frequency error of an oscillator continuously. So it needn't be a discrete-in-time measurement, and you can certainly measure errors of much less than one second on a 1 Hz signal. And your corrections certainly do not need to be discrete-in-time updates or, more importantly, corrections needn't come in multiples of 1 second.

Updating physical clocks or correcting for their drift doesn't have to happen like leap seconds do for UTC (which tracks TAI on the sub-second level but tracks astronomical time as far as which second it is, to within 0.9 seconds.)

So if you have an oscillator that should be running at 1 Hz, and it started out that way, but it is slowing down at PRECISELY the rate of 1 Hz per hour, you could theoretically apply a constant 1 Hz per hour correction to the oscillator (after bringing the oscillator back to 1 Hz), and then the oscillator would be perfect at all times.

There is no inherent advantage to performing this process with a 4.5 GHz oscillator as opposed to a 1 Hz oscillator.

Re:this will benefit lower freq apps too

[Atario]

I would think you would calibrate the clock before you start dividing -- measure how many ticks you get in ten seconds, divide that number by 10, and divide your clock's output by that. Might be 998 on this one, 1003 on the next one.

Still would be better the higher your starting frequency is, of course, since even if you calibrate perfectly, you still might be off by 0.5 ticks, but that 0.5 ticks represent less and less of an error the more input ticks you're counting per output tick.

Re:this will benefit lower freq apps too

[Bombula]

I thought accuracy and stability of resonators depended on properly using the phase discriminators to align the resonators to within a 0.5% frequency variance of the warp core. Did I miss something?

Re:this will benefit lower freq apps too

[imgod2u]

The main advantage here is self-clocking chips with high frequency requirements. Typical low-frequency chips either can live with an external oscillator, are clocked by another control chip or aren't very frequency-dependent and use internal ring-oscillators.

Re:this will benefit lower freq apps too

[Anonymous Coward]

Cornell isn't there first.

http://www.sitime.com/index.htm

Re:this will benefit lower freq apps too

[v1]

That stage is where you are trying to make the end cycle as accurate as possible. If you can say, get a resonator to slip one or two cycles per a given period, it's to your advantage to go for a higher clock rate, and then divide down. When you divide down, you also divide down the error. So if your resonator might slip +/- 4 cycles in a period, and you are dividing it down by 8, then resulting signal may slip +/- 0.5 cycles per the same period.

Great news

[vectra14]

I really hope these guys make it as integrated MCU modules soon. I can't claim that I've ever designed *really* small stuff, but I have some experience designing rather compact sensors,etc: the external crystal that drives the (I'm talking something between 20 and 200Mhz) MCU/DSP in these settings is typically almost as big as chip itself! It gets worse since typically you have to add discrete caps specifically for the xtal type/frequency and the whole thing makes your pretty, tiny, elegant, simple circuit that much more needlessly complicated.

Neat

[tsa]

That is a fine piece of microengineering they show there! I'm impressed. I have one question, however: in the article it says: The Q factor for the Cornell device at 4.51 gigahertz is close to 10,000, which compares well with quartz resonators. Does that mean that although the frequency at which the device vibrates is higher than quarts, the accuracy is about the same?

Re:Neat

[The Living Fractal]

I believe you are correct. Which basically means that for any given frequency compared to what you would have from quartz you will get a finer, more statistically predictable waveform.

Re:Neat

[Antique Geekmeister]

No. While the frequency published is "clean", it's vulnerable to manufacturing skew, thermal drift, and other issues that will create skew in the clock. Quartz is useful because it's thermally and mechanically stable, due to being a crystal with a low thermal expansion coefficient and mechanically easy to machine within quite small tolerances.

Re:Neat

[cats-paw]

The Q is an indicator of the short term accuracy of the resonator. The long term accuracy is usually discussed in terms of temperature drift. The absolute accuracy has to do with how accurately you can produce a resonator of the desired frequency.

The short term accuracy is referred to, by digital designers, as jitter and is a very important figure of merit in both digital designs and communication systems.

The Q of this resonator is quite good, athough it's not unusual for quartz crystals to havo a Q of 50000. What's truly amazing is that this resonator has a Q of 10000 @ 4.5 GHz. The high end on a quartz crystal is in the range of 20 to 40 MHz. It is very difficult to produce resonators with such a high Q at such a high frequency.

Re:Neat

[dbateman]

If you used a frequency divider chain to bring the frequency down to the same as that of a quartz resonator, or if you expressed the noise from the oscillator in terms of a jitter then yes. However, the phase noise of an oscillator goes up by 3dB for each doubling of frequency, and there is a well known relationship between the Q-factor and the phase noise and a doubling of the Q-factor gives you 6dB of improvement in your phase noise. However, without knowing more its not easy to convert from the Q-factor to a phase noise number..

For a system with 802.11a you need about -110dBc/Hz of phase noise at 1MHz offset. OFDM systems like 802.11a are a bit special with respect to the phase noise as the OFDM modulation (in particular the OFDM pilot tones) is designed to correct for the phase noise that is closer to the carrier than an OFDM carrier spacing (ie about 300kHz). Therefore a really interesting application for such an oscillator is inclusion on chip of the high-Q oscillator for WLAN/Cellular radios, where current commercial designs typically have at least the tank of the VCO off chip. Though for that the oscillator needs to be tunable, and I'm not sure these designs are.

D.

Re:Neat

[EEmarty]

That is exactly correct. The Q of a resonator http://en.wikipedia.org/wiki/Q-factor#Electrical_systems/ or oscillator determines it's efficiency at turning electrical energy into a usable oscillation. The real significance of this new resonator is that it can be incorporated into the same piece of silicon that the electronic circuit is built on. Currently if a circuit needs a high quality clock or RF signal it uses an off chip crystal oscillator to generate a reference clock usually at 10s to 100s of MHz and then multiplies it up to the frequency needed on chip with an on chip Phase Locked Loop (PLL). PLLs work great, but they take up valuable area and power. Also they are one of the few analog circuits left on most modern microprocessors so it is expensive to keep specialized analog engineers (of which i am one) on staff to design the PLL. If this oscillator/resonator works as described and can truly be integrated into advanced CMOS manufacturing processes, it would eliminate the need for an off-chip quartz crystal and reduce the cost of the system. You probably have about 15 quartz crystals inside your computer now humming along at different frequencies to create the reference clocks of your cpu, memory, pci bus, cdrom, display, wireless, bluetooth, etc. These could potentially all be removed significantly reducing the cost of a computer system and other electronic gizmos. It could also reduce the size and increase battery life of handheld wireless devices. Whether it lives up to the hype that the researchers and reporters of technology review are creating is the big question. Martin

Re:Neat

[Anonymous Coward]

foolish poster - the upper range for quartz resonators (now) is ~ 2.5 Ghz (3rd ot). practically (in production) ~ 600 MHz -
cake walk 155 MHz

Re:Neat

[John Miles]

However, the phase noise of an oscillator goes up by 3dB for each doubling of frequency

6 dB (or 20*log(N)).

Re:Neat

[karlandtanya]

No, the Q factor of a resonator tells you how much of the standing wave's energy stays in the cavity.

Re:Neat

[LM741N]

i saw the post above about a Q of 10,000. Thats pretty high for the freq's involved. Q= 3dB bandwidth/frequency for resonators. But for HF, its very low. When they made HF (ie 1Mhz to 30Mhz) crystals for filters in the US, Q's were 100,000 or so. The crystals you get now days are so bad that you are lucky to find one out of 20 that has a Q of 50,000. There were special crystals used in certain applications with Q's of a million, but they are no longer made. What makes crystal Q so important is that the loss of a filter made with the crystals depends on their Q. The lower the Q, the higher the loss of the filter. For VHF up through microwave you want as low a system noise figure as possible, and high loss filters just makes the task very hard.

Re:Neat

[dbateman]

Opppss. Yes.. Typed too quick

D.

Quartz is Silicon

[Doc Ruby]

Traditional quartz crystals are also made of silicon (SiO2). Silicon is the most abundant element in the Earth's crust, quartz the most abundant mineral. It's a lot cheaper than these new nanofabricated resonators, though the new ones are also made of silicon.

Re:Quartz is Silicon

[norton_I]

No, quartz is silicon dioxide.

Re:Quartz is Silicon

[Doc Ruby]

Er, silicon dioxide is made of silicon (and oxygen): "Si02" is "silicon dioxide", as I said. So is this new "silicon resonator" (and everything else made of "silicon chips").

Re:Quartz is Silicon

[Anonymous Coward]

No, quartz is silicon dioxide. Would that perchance be why he wrote "(SiO2)"?

Re:Quartz is Silicon

[imgod2u]

CMOS is silicon-dioxide as well......or at least the substrate is.

The point here is that instead of a discrete chip using a different fabrication process, a resonator can be built on a standard CMOS process. The article is very short on details of how this thing actually works but I was under the impression that we had such a technology already. It's called a ring oscillator....

And it's mechanical

[Animats]

Mechanical vibrations at 4.5GHz. Just think about that for a moment. A tiny piece of silicon, like a little tuning fork, wiggling back and forth 4,500,000,000 times every second. Without breaking or wearing out. It's not just electrons moving; this is a solid piece of material vibrating.

Re:And it's mechanical

[Jeff DeMaagd]

Some of the macroscopic things that we understand almost intuitively don't hold very well in the micro world. For example, DLP projection uses mirrors that twist on a sliver of aluminum hundreds of times a second, but they're reliable for many billions of actuations.

Re:And it's mechanical

[ByteSlicer]

All matter vibrates, and usually at a much higher frequency. It's called temperature. The reason larger structures break, is because they often contain tiny flaws in their structure (crystal lattice) that get bigger with each bend. The smaller the structure, the less probable there is a flaw. And the silicon wafers are a single crystal to begin with.

I's be more worried about frequency drift because of thermal fluctuations.

Re:And it's mechanical

[Quato]

Mechanical vibrations at 4.5GHz. Just think about that for a moment. A tiny piece of silicon, like a little tuning fork, wiggling back and forth 4,500,000,000 times every second. Without breaking or wearing out. It's not just electrons moving; this is a solid piece of material vibrating.

Is it just me, or does this comment read like really nerdy soft core porn?

All depends...

[Anonymous Coward]

Its usefulness depends somewhat on the temperature coefficient of the natural frequency, the 'Q' of resonance will determine how easily and quickly an oscillator starts, and finally the repeatability in the manufacturing process. Some level of variation due to temperature can be compensated for by including temperature sensors on the substrate. It will be quite a challenge to get the yield up on this but will be an enabling advancement for many new features and higher integration.

CPU clocks

[martyb]

Also, multiple resonators of different frequencies could be put on the same chip...

Could this lead to improved performance for CPU/GPUs? My understanding is that there are parts of a chip that cannot keep up with the rest of it and the slowest part ends up being the one that sets the clock speed. Let's say some part(s) of the chip can handle being clocked at 4.5 GHz. But, other parts could only handle 3.0 GHz.

Instead of clocking the whole chip at 3.0 GHz, one could put multiple resonators on the chip and let part(s) run faster than the rest. This would be a hybrid of the current fully-clocked chip (and all the attendant problems with propagation and synchronization of the clock) and of a clockless chip (which has its own design constraints).

Of course, this would make it even more "interesting" to try and figure out just how fast a chip is: The Intel mulberion (TM) processor is clocked at up to 4.5 GHz (that we only use for one part of the chip; the rest runs at 1 GHz but it sounds much better this way.

Blegh. Might as well call it a need-a-clue-clue-clock. ;^)

Re:CPU clocks

[marcansoft]

Clocking different parts of a chip with separate completely independent clocks is a bad idea, because then different parts of the chip are in different clock domains. This causes metastability problems when the drifting clocks periodically align to violate the timing constraints of the other side of the circuit. Then you need synchronizing circuits, which add delays and don't guarantee anything (the more you wait, the more you reduce your chance of failure, but there is always a chance).

Re:CPU clocks

[noidentity]

No, since we already have phase-locked loops to generate the 4.5 GHz or whatever clock, and dividers to turn that into 3.0 GHz. As I understand it, the only benefit of this new resonator is increased frequency accuracy, which wouldn't matter in a PC.

Re:CPU clocks

[martyb]

Clocking different parts of a chip with separate completely independent clocks is a bad idea, because then different parts of the chip are in different clock domains. This causes metastability problems when the drifting clocks periodically align to violate the timing constraints of the other side of the circuit. Then you need synchronizing circuits, which add delays and don't guarantee anything (the more you wait, the more you reduce your chance of failure, but there is always a chance).

Thanks for the explanation; I think I see what you're saying. Bad Things can happen when things get out of sync. But I'm having trouble reconciling this with how, for example, a GPU doesn't run (generally) at the same clock as the CPU, and yet they (seem to) get along just fine.

I grok software a lot better than hardware, so please bear with me. Let's say I've got two chips. Chip1 wants something done. Chip2 will do it for me. Chip1 sends the command and data out to Chip2. But, Chip2 waits until Chip1 has set a line on Chip2 to indicate that it is ready for processing (Data Ready or something like that). It's only THEN that Chip2 does its thing. When Chip2 is done, it puts the result on its outputs to be read by Chip1. Chip1, similarly waits for Chip2 to set its Result Ready line so that Chip 1 knows it's safe to read the result.

Can't these chips have different clocks? They just wait for the appropriate line to toggle and then they know they are good to go. So, if that's the case, just put these two "chips" on the same piece of silicon and use this new clocking mechanism to give them whatever the fastest clock is that they can handle. Let's say it takes 100 ticks for Chip2 to do its thing. But, it's simple stuff and it can be clocked 20% faster than what Chip1 can handle. Seems like a net improvement to me.

Think of it as a Beowulf cluster on a chip. One can use systems with different clock speeds in a cluster, can't something similar be done on a single chip?

Re:CPU clocks

[LarsG]

But I'm having trouble reconciling this with how, for example, a GPU doesn't run (generally) at the same clock as the CPU, and yet they (seem to) get along just fine.

That's because the CPU and GPU are not as tightly coupled, you have at the very least a PCI/PCI-E/AGP bus between them.

To do the same inside a single chip, you need to define a communications interface between the separate modules. It is really a cost/benefit thing, you will gain performance by having some parts of the chip running at a higher clock but you will have to spend transistors on implementing the interfaces.

Re:CPU clocks

[hebertrich]

Nice in theory .. there's many obstacles to such a
gadget.One of the most important factors aint frequency.
it's stability . good quality crystals need to be in small
ovens to keep the frequency stable. Is the frequency changing
with temperature ? If so does it need the chip to be kept also
at a very specific temperature ? How about repeatability ?
By using the production technique they have ,can they make two
parts oscillate at the same frequency as easily as crystals ?

BTW .. as much as you can devide with oscillators based on crystals
you can use frequency multipliers to acheive the higher frequecies ..
but the problem is always the same .. drift.

All nice details the engineers might/might not be able to solve for out
the lab use.

New technologies are nice in only one case : when they work out the lab.

Cheers

Re:CPU clocks

[imgod2u]

This is already done. Very few microchips nowadays only operate using one clock. Internally, the main clock (or in some cases multiple main clocks) are gated or divided down to drive lower-frequency components (albeit multi-cycle paths are used more often). The case you mentioned of a critical path running too slow can be alleviated by using multi-cycle paths.

The problem, however, is that the rest of the chip still has to wait for the results from that critical path. Whether it's clocked slower, or allowed 2+ cycles to settle, the rest of the circuits still have to wait. So you could clock it up however fast you want but it's not going to change the fact that that one little critical path will halt the data flow.

Old crystals - once common in ham radio

[Cliff Stoll]

This article inspired me to dig out my ham radio crystals from the 1960's.

"Rock-Bound" ham radio transmitters could only send messages at one frequency, so amateur operators sometimes modified the crystals to change frequencies. You'd tune the quartz crystals by grinding them with fine powder -- a few swipes would change frequency from 7130 to 7133 KHz (called "KiloCycles" back in the dark ages of the 1960's).

I just photographed a couple such crystals and put them at http://picasaweb.google.com/BoomingHand/HamRadioCrystalsFromK7TAOnceWN2PSX where you can see the primitive technology. The quartz itself is about a square centimeter and maybe a half millimeter thick.

All of this was made obsolete by quality variable frequency oscillators, often using phase-locked loops.

I'm thrilled to see the 4.5 GHz resonators at Cornell ... all the more so for having fooled with quartz crystals forty years back.

The rules change at small scales

[Animats]

That's true. I was once talking to one of the first designers of ink-jet printers at HP, and he mentioned that intuition about fluid behavior totally fails at that scale. They had to do simulations that modeled the interatomic forces to make inkjets work well.

Is that...

[kcbanner]

Is that your Silicon Resonating or are you just happy to see me?

Battery consumption

[Yocto Yotta]

"In a cell phone, for example, high-frequency resonators could filter out interference from other sources of radio signals." I'd be willing to bet this would have a benificial impact on battery performance. Small or large, I don't know.

Major Issues

[LM741N]

1. What is the temp coefficient for these devices? If it high, they will be essentially useless for communication usage, esp wireless and microwave.

2. If they ever get into mass production, what is the projected cost per unit?

I see these devices possibly used as clocks for computers, but why buy something exotic like this when you can just use a PLL that costs $0.50 ?

Re:Major Issues

[LM741N]

I forgot one other important parameter- Q. if the Q of the resonator is low, they will be useless in filter applications. Sometimes oscillators won't even start if the crystal Q is too low.

Re:Major Issues

[ChrisMaple]

Another question is how bad the spurs (secondary resonances) are. This is important for filters; for oscillators you generally don't care.

Re:Major Issues

[msheekhah]

didn't the amiga use out of order bus execution that allowed for tremendous speeds, it could emulate a mac on top at speeds faster than a mac ran, but on the same hardware? wouldn't it be possible with these to design out of order execution due to dyssynchronous internal bus speeds, and acheive massive improvements in performace, both at the chip level, and at the pci controller/mobo level?

Radio recievers

[Anonymous Coward]

Several of these running at different frequencies would make very efficient IF (intermediate frequency) stages in radio tank circuits. Explained basically, a transmitted signal is modulated by a high frequency signal. You can't hear with your ears in the gigahertz region, so the signal is mixed (in a mixer circuit) with a source signal from a tank circuit. The mixer circuit creates both sum and difference signals. Example 1 million cycles per second radio (or television) broadcast (modulated with sound ranging from 60 Hz to 20 KHz giving a signal in the range of 1000060-1020000 Hz, mixed with a tank circuit frequency signal of 1000000 cycles per second will generate sum signals of 1000020-1020000 Hz (sum frequencies) which are usually filtered, and 20-20000 Hz (which are amplified and sent to a speaker. One or more 'IF' stages are used in these mixing 'superheterodyne' receivers. Having several stages on one chip makes creating wideband receivers much less expensive.