Larrabee Based On a Bundle of Old Pentium Chips
arcticstoat writes "Intel's Pat Gelsinger recently revealed that Larrabee's 32 IA cores will in fact be based on Intel's ancient P54C architecture, which was last seen in the original Pentium chips, such as the Pentium 75, in the early 1990s. The chip will feature 32 of these cores, which will each feature a 512-bit wide SIMD (single input, multiple data) vector processing unit."
Larrabee is the codename for a discrete graphics processing unit (GPU) chip that Intel is developing as a revolutionary successor to its current line of graphics accelerators. The video card containing Larrabee is expected to compete with the GeForce and Radeon lines of video cards from NVIDIA and AMD/ATI respectively. More than just a graphics chip, Intel is also positioning Larrabee for the GPGPU and high-performance computing markets, where NVIDIA and AMD are currently releasing products (NVIDIA Tesla, AMD FireStream) which threaten to displace Intel's CPUs for some tasks. Intel plans to have engineering samples of Larrabee ready by the end of 2008, with public release in late 2009 or 2010.[1]
According to Wikipedia http://en.wikipedia.org/wiki/Larrabee_(GPU)
Taxation is legalized theft, no more, no less.
Get your acronyms right....
No sig today...
Power can come from multiple sources. In this case, you have a 150W power connector (probably a 6pin PCIe one), and another 75W one (yet another 6pin PCIe). The remaining 75W comes from the PCIe connector itself.
Nothing terribly unusual - a number of cards are coming out in configurations like this, and 300W for a video card is starting to become the norm, depressing as it is.
Not quite...
Larrabee is a general purpose number cruncher with high degree of parallelism.
NVIDIA/ATI are moving towards making their graphics cards capable of running general purpose code. Intel is coming from the other side, moving a general purpose parallel-compute engine towards doing graphics.
Yes it's a subtle difference and yes they'll meet in the middle, it's just a question of angles.
Intel wants the parallel compute market more than it wants the graphics card market so that's who it's pitching this at.
No sig today...
I don't care if you're a C64 fanboi, Pentiums made mistakes. Apple had nothing do to with it. Read here.
And this also from the same source... "In June 1994, Intel engineers discovered a flaw in the floating-point math subsection of the Pentium microprocessor. Under certain data dependent conditions, low order bits of the result of floating-point division operations would be incorrect, an error that can quickly compound in floating-point operations to much larger errors in subsequent calculations. Intel corrected the error in a future chip revision, but nonetheless declined to disclose it."
The original Pentium (which went to 166Mhz, at the end, not just 75Mhz), used U and V execution pipes. No translation to micro-ops, and no "out of order". Indeed, there shouldn't be a need for that in Larrabee, anyway, given the number of cores. It would almost be better to get rid of the V pipe, and add SIMD, instead.
Your comments on CISC are bit off-base; the idea is to execute shaders in x86 machine code. They can be simple (limited flow control), or complex (general CPU/GPU).
"out-of-order" (ei. Pentium Pro and better) is not so good with that many cores doing that kind of work. It would get the hardware into a lot of trouble. Better to keep it simple, and add more cores.
A better start point would probably have been ARM, but that would lose the compatibility edge. If Larrabee works, it will take the GP-GPU market by storm. It needs:
1 - to publish itself as an NUMA access CPU (add a bit to tell the OS what it is for)
2 - compiler optimizations for the particular CPU architecture, preferably broken into two pieces:
2a - "straight line" shader code
2b - branching code
3 - a guide to the new NUMA characteristics.
With that in place, a standard (BSD/LINUX) OS will be able to use it for regular jobs. Or, for those special "I need the SIMD unit" jobs. The biggest hassle is trying to split control of those new CPU units between OpenGL and the regular scheduler (this is a kernel hack that Intel will have to make). It would be easier to jam this into OpenSolaris, but that isn't anywhere near popular enough.
Don't you want your video card to assist compiling large source when not gaming/modeling? Why not?
And, a few "extra" points
- Intel already has an optimizing compiler for the P54C architecture, and we have gcc.
- The architecture, including U/V pipelines only used 3.1 million transistors.
- A GeForce 7800 GTX has 302 million transistors -- 100x the number of the original Pentium processor.
So, I would think that using 32 "Pentium Classic" cores reduced would be quite feasible -- you need some (lots) of logic to ensure that they can all access their respective memories. The general SIMD implementation will take quite a bit of real estate as well. There is probably a budget of 600M transistors (wild ass guess) to Larrabee, estimate derived from power consumption estimates.
The gate size shrink should result in higher speeds. There may be a danger in the complex instruction interpretation routines, but these can be corrected. The single cycle instructions are already a (more than less) synchronous design, and should scale trivially.
Anything I am missing?
I, for one, am looking forward to buying a desktop super-computer with Larrabee.
Just another "Cubible(sic) Joe" 2 17 3061
Yes, 32 x 600MHz x 1MIP/MHz @ 0.5W == 19.2 GIPS@16W.
Meanwhile...
32 x ???MHz (Unknown, but likely to be 900+ to be competitive with current designs) x 3+MIPS/MHZ + 32 x 512-bit SIMD units = OMGWTFHAX @ 300W.
Seriously. The "Pentium" base of this design is damned near irrelevant. At this point, all it's doing there is scheduling execution on the SIMD units. If you've seen any modern GPU designs, they're basically hugely parallel cores attached to a few "director" cores which puts everything where it needs to go. The original Pentium is probably the most powerful CPU with the least complicated design on the process, with the least amount of legacy MMX cruft.
"Victory means exit strategy, and it's important for the President to explain to us what the exit strategy is." G.W.Bush
http://babelfish.yahoo.com/translate_url?doit=done&tt=url&intl=1&fr=bf-home&trurl=http%3A%2F%2Fwww.heise.de%2Fct%2F08%2F15%2F022%2F&lp=de_en&btnTrUrl=Translate
Actually, they got the "Gelsinger said so" remark from Expreview, itself a Chinese site:
http://en.expreview.com/2008/07/07/larrabee-unleashes-2-tflops-capacity (note they curteously attached the Larrabee board diagram leaked from a while back):
"Gelsinger said the Larrabee will be a 45nm product featuring SIMD technique, 64-bit address. Besides, 32 of cores runing at 2.00 GHz will unleash 2 TFLOPS capacity, twice as much as the RV770XT."
But did Gelsinger really SAID those things?
Here is the Google translation of the same Heise article: http://translate.google.com/translate?u=http%3A%2F%2Fwww.heise.de%2Fct%2F08%2F15%2F022%2F&hl=en&ie=UTF8&sl=de&tl=en
It seems that no matter which crappily translated version of the German article one looks at, it appears that Gelsinger said no such thing... The part about Larrabee containing P54C cores was clearly in a separate paragraph, written after a speculative question.
So I guess Expreview THOUGHT Pat said something after it took a too-short of a look at the Heise article, after which CustomPC sensationalized the whole thing, not really bothering to actually read even the translated link it posted. Now, some random Slashdotter is doing the same curtesy.
There you go, folks- Internet reporting.
It wasn't every time you divided. It only affected floating point operations, and Intel claims that only 1 in every 8.77 billion random divisions will show the error, and those familiar with the bug agree that Intel's analysis is more or less correct. That would explain how it got through the initial testing by Intel and that the bug wasn't noticed for a while by the general computing public. The whole thing was more of a PR disaster on Intel's part than anything else.