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Lawsuit Claims Nvidia Execs Concealed Serious Flaw
snydeq writes "A lawsuit filed in a California court on Tuesday alleges Nvidia concealed the existence of a serious defect in its graphics-chip line for at least eight months 'in a series of false and misleading statements made to the investing public.' The lawsuit contends that Nvidia CEO Jen-Hsun Huang and CFO Marvin Burkett knew as early as November 2007 about a flaw that exists in the packaging used with some of the company's graphics chips that caused them to fail at unusually high rates. Nvidia publicly acknowledged the flaw on July 2, when it announced plans to take a one-time charge of up to $200 million to cover warranty costs related to the problem. That announcement caused Nvidia's stock price to fall by 31 percent to $12.98 and reduced the company's market capitalization by $3 billion, the lawsuit said. The lawsuit seeks class-action status against Nvidia and unspecified damages."
"Frankly, this whole fiasco just strengthened my love for ATI. Their newer binary blobs are amazing."
Quick! Someone frame the above. I never thought I'd see the day when someone said something nice about ATI drivers.
sign up
you'll probably end up getting a coupon for a free software widget that lets you adjust the contrast settings from the system tray
the lawyers, on the other hand, will be getting $70M
Nope, it seems that the cardboard box they were shipped in contain a high level of a rare Iridium isotope that causes molecular decay of the technology in the Nvidia chip. Nvidia runs on Logic diamonds and logic diamonds exposed to Iridium 237 causes rapid decay and failure.
If they would have had the packaging done in the USA instead of china things would have been ok.
NOTE: there is no danger to the consumer, the paint on the outside of the boxes has high amounts of lead in it, shielding you from the Iridium 237 radiation.
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Thanks!
Do not look at laser with remaining good eye.
Psh...AC isn't new. You must be new here!
"If someone could explain in non-layman's terms what exactly the problem was I would much appreciate it."
nobody else caught your request for 'non-layman's terms' so here goes:
Chip Scale Packaging (CSP) Technology
The information presented in this chapter has been collected from a number of sources describing CSP
activities, both nationally at IVF and reported elsewhere in the literature. The most important of the former
being the Chip Scale Packaging Task Force, an international multi-client programme carried out between
1996 and 1997 and a project work carried out by two students at Chalmers University of Technology..
D1. Introduction to CSP Technology
D1.1
Definition of CSP
Originally, CSP was the acronym for Chip Size Packaging but very few packages are of true chip size.
Therefore, the acronym is today usually used for Chip Scale Packaging. According to IPC's standard J-STD-
012, "Implementation of Flip Chip and Chip Scale Technology", a CSP shall have an area of
no more than 1.2X the area of the original die size and is direct surface mountable [D1].
D1.2
Description of various types of CSPs
In contrast to most other package types, the name of the package type, "Chip Scale Packaging", contains no
information about how the package is constructed, except for that it shall have approximately the same size
as the chip. Therefore, CSPs include component types with probably more dissimilar characteristics than
any two other IC package types clearly manifesting the inaccuracy to look at CSPs as a homogenous group.
Some packages look like miniaturised BGAs which names like miniBGA and BGA indicate. Others have
leads which give them properties similar to conventional leaded packages such as PLCCs. For this reason,
CSPs are often classified based on their structure. At least four major categories have been proposed [D2].
These are: flex circuit interposer, rigid substrate interposer, custom lead frame, and wafer-level assembly.
Examples of packages of these categories are given in Figure D1.
Chip
Sealing Resin
Lead Frame
Wire Bond
Tape
Protective
Layer
Custom Lead Frame
Package by Fujitsu
Rigid Substrate Interposer
Package by Matsushita
Chip
Sealing Resin
Land pad
Ceramic Substrate
Via
Stud Bump
Flex Circuit Interposer
Package by Tessera
Chip
Ring
Lead
Flex Tape
Bump Array
Elastomer
Wafer-Level Assembly
Package by ChipScale
Metal Cap
Epoxy
Metal Lead
Metal Plated Silicon Post
Silicon Circuit
Figure D1. Main CSP Categories
D1.3
Driving Forces for using CSPs
The main driving forces for using CSPs are:
Improvement in performance
Size and weight reduction
Easier assembly process (compared to bare die attach)
Lower overall production costs.
Of these, reduction of size and weight are probably the most important factors for initial adoption of CSP
technology. Consequently, consumer products like camcorders, mobile phones, and laptops are among the
products that have been first to utilise CSPs.
D1.4
Advantages and disadvantages using CSPs
Chip Scale Packaging combines the best of flip chip assembly and surface mount technology. It gives
almost the size and performance benefits as bare die chip assembly, at the same time as it offer the
advantages of a encapsulated package. CSPs can be standardised, tested, surface mounted, and reworked.
So far most CSPs have been produced for applications with rather low number of I/Os but many types of
CSPs can be produced with large number of interconnections. However, before CSPs with large number of
I/Os will find widespread use, techniques for producing reliable low-cost high-density printed boards must be
developed.
The advantages and disadvantages of CSPs depend on what one compare with, standard surface mount or
bare die assembly. Due to the large spread of characteristics for various CSPs, it also depend on the type of
https://www.gnu.org/philosophy/free-sw.html
Double Lifetime Warranty, eh? So, from now until you become a vampire, and then from that point on until some skinny blonde girl stakes you?