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Intel Unveils 6-Core Xeon 7400
JagsLive recommends CNet coverage that begins "Intel officially unveiled its six-core 'Dunnington' Xeon 7400 processor Monday ... As expected, Intel launched the Dunnington chip for high-end servers ... The Xeon 7400 is also one of the first Intel chips to have a monolithic design. In other words, all six cores will be on one piece of silicon. To date, for any processor having more than two cores, Intel has put two separate pieces of silicon ... inside one chip package."
I'm betting new Mac Pros will be launched today.
There is no need for a base two if you are adding. You add cores, you do not multiply them.
2, 3 (yes, triple code do exist), 4, 6. I guess the next step will be 8 and perhaps even skip that and make it 9 (3x3).
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see amd ... they have 3 cores in one chip and the shit fares prety well
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"There's an odd catch, however, that will affect the highest of high-end configurations. "Because Microsoft Windows operating system support is limited to a 64-core environment, within a single OS instance, we'll support up to 64 cores," said Colin Lacey, a Unisys marketing vice president."
Gads, who on earth would run a 64-core Windows box? Unless they want to virtualize out multiple servers on one bit of hardware. Most of the "heavy lifting" I've seen on servers with mucho processor cores are running some flavor of Unix. I'm kinda surprised this hasn't been fixed already given the momentum of multi-core processors.
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Is it just me, or does 6 seem like a counter intuitive number of cores ?
Remember they need to put other stuff on the silicon too. The XBox 360's CPU uses three quarters of the die for three processors and puts the shared cache etc. in the fourth quarter. Six + support circuitry probably fits a square die better than eight + support.
No, it just matters that you have more than one.
Sun had 8-core server CPUs since several years now. They didn't have any problems allocating the die's surface.
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Of course their die surface is 8 times bigger too.
> there is usually a requirement for an even number
> of cores in SMP (symmetric multi processing)
Why?
You have tasks [A, B, ... I], and you run task A on first core, task B on 2nd, ... task I on ninth. What kind of black magic could possibly hold me back from scheduling nine tasks to run on nine cores? CPU scheduling is CPU scheduling, isn't it? The last time I've checked, you can build a Linux kernel with support for anywhere from 1 to 255 CPUs. Or should I insert "assert((num_cpus%2)==0)" everywhere in my hypothetical homebrew hobby OS?
I think the "symmetric" in SMP means more like "parallel".
The "symmetric" in SMP refers to all CPUs being identical, not to the actual number of processors.
Symmetric multi-processing refers either the generally the type of cpus, i.e. all processors have the same capabilities, or to their relationship with memory. SMP is generally shared memory systems with a set of uniform processors.
http://en.wikipedia.org/wiki/Symmetric_multiprocessing
Any decent host is also going to kill you for bringing more power to your rack so there is definitely a balancing point. The fact is that the datacenter is designed for a certain power density and going beyond that really screws things up. Airflow and cooling densities, percentage of space allocated to UPS and generators, etc. But, looking at the Intel press release, these suckers pack 6 cores into a 65W power envelope, quite impressive. This compares quite favorably with the 45W for the best current generation quad cores, so total system power per computation should improve quite a bit. Now if only we could get Intel to get away from using power hungry FB-DIMMS.
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6 = 8 - 2 broken cores ?
You joke but that's already the case with PS3's Cell (7 SPU = 8 - 1 broken), with tripple core Phenom (3 = 4 - 1 broken), and with a very high number of graphic cards (The range segment {pro/mid/low-cost} on which a GPU is used = the number of functional cores they managed to salvage)
A separate reason may be the number of {quickpath/hypertransport/etc.} interconnects (6 cores require 15 interconnect to communicate, 8 cores require 28 interconnects). 6 to 8 cores isn't such a big increase but keeps the number of inter connect reasonnable.
(Other processors types like Tilera end up only interconnecting adjacing cores on their 64x chips and you have a strongly *Non*-Uniform Architecture, with not all core able to reach and talk to others at the same speed)
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That has nothing to do with symmetric multiprocessing. SMP means that all the chips can make memory accesses to all the memory at the same speed. It is the opposite of Non-Uniform Memory Access, or NUMA, in which certain processors (some or all of them) take longer to talk to certain parts of main memory than others or systems in which processors have a faster path to some private off-chip memory in addition to the main shared memory.
That's no different from the 486SXes, many of which were 486DX parts with the defective math coprocessor diked out. It's not very different from how the clock rate on every mainstream chip is determined by how many chips turn out to be stable at which speeds.
In the article it's pretty clear this is a legacy-at-launch part to be a last upgrade for people using the current FSB technology. Other products will use QuickPath, but this is for those who want to keep their current motherboards for one more generation of processors.
"Why would they start working on a new chip that moves it off again?" Please! They are not moving it off again! Please understand! This is an upgrade to their exististing Xeon MP server design and these chips can fit into _existing_ servers. There will be new Xeon MP chips based on Nehalem ready late next year. Xeon MP chips takes much more time to validate that desktop chips.
There wasn't much in terms of technical specs in TFA. 6 cores, 16MB cache, anything else? Clock speed? 16MB of L2? L3? FSB? DDR(n)? (Though this is probably more up to the MB manufacturer) Why are they moving the memory controller off silicon? That in itself seems like a step backwards.
Pentiums have never had an on-die MMU in the first place, they're actually doing that for the upcoming Nehalem. AMD has used an on-die MMU since the Athlon 64, and while it certainly helps squeeze more efficiency out of the system, the faster clocked bus on Intel rigs often made up for the theoretical performance gap.
The Clock speed was omitted from the article, but the Xeon 7400 is clocked at 2.6ghz. That's actually pretty decent for a Xeon, they don't go as high as the mainstream processors because they're made to be installed in a puny rack chassis with piss-poor airflow.
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