Slashdot Mirror
IBM Leapfrogs Intel With 22nm Chips
Slatterz writes "Intel may be touting 45nm CPUs, but IBM says it can go much further with a strategy to produce future chips using a 22nm fabrication process. The company is adopting a technique called 'computational scaling' in order to manufacture circuits small enough to deliver more powerful and energy-efficient devices. Intel plans to introduce 32nm chips in 2009, but chipmakers have hit a problem in that current lithographic methods are not adequate for designs as small as 22nm owing to fundamental physical limitations. IBM claims to have solved this problem." Unfortunately the phrase "computational scaling" doesn't actually convey any information about how they've solved it.
FTFA: "IBM said that computational scaling overcomes these limitations by using mathematical techniques to modify the shape of the masks and the characteristics of the illuminating source used to image the circuits for each layer of an integrated circuit."
That gives you an idea. They are not being more secretive than normal.
"Civis Europaeus sum!"
Via their press release: http://www-03.ibm.com/press/us/en/pressrelease/25147.wss
Because it isn't just the technology you develop. You have to get several other companies to align their technology roadmaps with you. Processing/handling equipment, raw materials, and a number of other technologies are involved in the production of a wafer.
The semiconductor manufacturing industry pretty moves together as a whole. Even if one company is out in front in terms of technology it isn't that far ahead, which is why so many companies just focus on design and have foundaries make their stuff.
D6 63 0D 70 89 81 BB 8E 7B 7C 5F 5D 54 EA AB 73
IBM and Intel have complete cross-site patent agreements. Anything that IBM patents in the future, Intel already has a license for -- and vice versa. Trade secrets, on the other hand, are legally protected as long as the company with the secret takes adequate steps for it to remain a secret.
Let me translate the press release:
We announce that our future product, someday in the undefined and possibly distant future, will hit 22nm. We're making partnerships to make it happen.
The slashdot writeup is misleading. For shame!
The linked page contains a flash ad that took over IE. It injected some chinese ad into other sites that also used flash.
Don't open this page in IE.
When you start designing a CPU, you have a transistor budget. Someone looks into their crystal ball and says 'in five years, when you've completed the design, we will be able to give you n transistors and sell the resulting chip in the market segment we want.' This is really hard to do for two reasons. The first is that it requires them to predict what the market will want five years in advance (the P4 was probably the biggest example of a miss-prediction here). The other is that they need to work out how fast the process technology will improve.
Moore's Law is usually used for the second part, but it's basically a self-fulfilling prophesy. The process people are told 'we need this transistor density in five years.' When they have made enough developments to get it down to that size, they start building the new fabs. If they go too fast then this screws up the core team because they suddenly have more transistors than they expect. Each chip is designed for a range of about a factor of two transistors. As process technology evolves over the core's life, they shrink it for the low end and bolt on a few optional bits at the top end (better vector units, more cache - basically anything they cut from the original design because they ran out of space). A bigger jump at the start of the run eliminates the headroom, and means they won't have an improved product in two years. It also may mean that the next process jump won't happen on time, so the current generation and next generation chips will have the same cost-per-transistor.
I am TheRaven on Soylent News
I remember reading in a business strategy book that at least when it comes to GPUs, companies don't bother to patent much since patenting something requires you to disclose too much and the technology advances so fast that by the time you have your patent, it's obsolete and worthless.
Most users are just fine with a fixed system on a chip with no PCI. (ram too if you could pull that off) If you want to reduce power and cost you'd place as much as possible on a single chip.
Chips like TI's OMAP series (found in the Nokia handhelds, OpenPandora, and a load of other things) have a CPU, DSP, GPU and a load of other things in the same die. They use a stacked-chip design so you can plug 128MB of RAM (256MB coming soon) on top of the package. Power usage is around 250mW.
How about a working variation of Hyperthreading?
Hyperthreading is a Intel's implementation of an idea that IBM brought to market first (based on an academic research project which produced the first prototypes, with the original designer now working at Sun). Sun and IBM have had it working for years. As have a few others. Unlikely in ARM chips, since the performance/power benefits in this space are worse than with multi-core (Cortex A9 allows up to 4 cores). It only makes sense for Intel in the Atom because it allows two context to share an instruction decoder, which reduces the cost of x86 bloat a bit.
How about hardware accelerated stacks?
x86 chips have had hardware accelerated stacks for well over a decade - rewrite an iterative algorithm with a software stack as a recursive implementation and you'll see a speedup.
MMUs that can handle a driver memory space
IOMMUs have been in Sun and IBM chips since they introduced 64-bit CPUs and wanted to plug in 32-bit PCI devices. Newer Intel and AMD designs also include them.
Advances in clockless processing?
Asynchronous designs have been floating around for a few decades but still don't deliver the kind of performance benefit that offsets the extra complexity (which equates to extra power usage).
I am TheRaven on Soylent News
That isn't how chip fabrication or design works at all.
Intel has three design teams, in three countries. They compete for the next Intel release. The israeli team won the Core/Core 2 Duo design. All the design teams were expected (and told) to keep Moore's law in mind as the miniaturization teams worked out the shrinking details. The Core/C2D was the most efficient processor for that many transistors.
The new 80 core machines are also coming out of the Israeli design team. These things don't even have (many) more transistors than a C2D. But each core is basically a streamlined Pentium 2 core (like the Core architecture), and they all share a large cache, and Apple has first dibs. Sweet.
After all, I am strangely colored.
only applies to published material.
I'm still in college and we have a big semiconductors lab, so we had to learn the basics of lithography in class. The problem that people are running into is that everything uses UV light, which theoretically can make details of 10nm (its wavelength) but this is incredibly hard. There exists, but not commercially viable, techniques which use x-rays (masking material an issue), electron beams and proton beams(deBroigle wavelength). If IBM got one of these to work commercially it would be a big deal. If they built a state of the art one of these and made some 10nm features, no big deal. Probably the single biggest issue is that they have to make a machine accurate enough to be exactly in the focal point of the beam(~0.1 nm) and the smaller the beam you are using, the smaller the focal point so making more precise machinery is as much of a limiter as small beams.
As someone who has worked with 130, 65, and 45 kits, I predict that working with 22 as a designer is going to be a huge mess. 65 was the last "normal" generation, where layout actually looks like you would expect. Starting with 45, you need to add lots of "dummy" devices in order to make layout printable. You open the layout for something as simple as an inverter and have a hard time actually finding the transistors. This makes manual layout all but impossible (or at least, take 10 times longer than it used to). Designers will be almost completely constrained to standard cell based designs, which will really hurt in high performance areas.