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IBM Leapfrogs Intel With 22nm Chips
Slatterz writes "Intel may be touting 45nm CPUs, but IBM says it can go much further with a strategy to produce future chips using a 22nm fabrication process. The company is adopting a technique called 'computational scaling' in order to manufacture circuits small enough to deliver more powerful and energy-efficient devices. Intel plans to introduce 32nm chips in 2009, but chipmakers have hit a problem in that current lithographic methods are not adequate for designs as small as 22nm owing to fundamental physical limitations. IBM claims to have solved this problem." Unfortunately the phrase "computational scaling" doesn't actually convey any information about how they've solved it.
If I figured out how to do something that would lay a serious hurting on my competition, I wouldn't exactly go around saying how I did it either.
FTFA: "IBM said that computational scaling overcomes these limitations by using mathematical techniques to modify the shape of the masks and the characteristics of the illuminating source used to image the circuits for each layer of an integrated circuit."
That gives you an idea. They are not being more secretive than normal.
"Civis Europaeus sum!"
Via their press release: http://www-03.ibm.com/press/us/en/pressrelease/25147.wss
What a joke of an article. Every semiconductor manufacturer has several generations of process in various states in the lab. Woo IBM's showing sneak peaks at 22nm!
...it sort of takes 3D transistors and all that, but we know how to do these things. It's all using standard silicon, it's CMOS it's extraordinarily well charictarized right? But we've got transistors running at 11 nanometers, I can show you photographs of them. We have the leakage issues but we've got a very good plan.
I met with an Intel VP for an interview a while back and talked about where things are going. He had some nice lab-pr0n of what the photos claimed were 11nm transistors. I believe it was said that was "about 15 years out", and meant to offer reassurance that Moore's Law still had a bit more time left to go.
Actually here, let me go dig up my transcript so I can get a proper quote:
You're going to see that platforms are going to continue to evolve. We're moving to a faster cadence. The processor cadence is about a two year cadence, in terms of process technologies. By the way this is interesting. We know how to do Moore's Law for about another fifteen years which we've never had that kind of length of projection before.
That was 2 years ago, early October 2006. Who leapfrogged what now?
Introducing the new Occam Fusion! Now with sqrt(-1) fewer blades!
A fab is huge, most of the people who work on a site are completely ignorant of the details of how such deep magic is performed, most of those thousands are only concerned about keeping the xyz network up or replacing/upgrading servers in the datacenter.
Many of the machines are closed units which only ever get opened by a small number of techs.
Actual knowledge of how they do what they do can be kept between a surprisingly small group of people.
Yes someone could take a stab at it but much of the time it's the fine details rather than the general idea that make an idea workable.
Most users are just fine with a fixed system on a chip with no PCI. (ram too if you could pull that off) If you want to reduce power and cost you'd place as much as possible on a single chip.
Chips like TI's OMAP series (found in the Nokia handhelds, OpenPandora, and a load of other things) have a CPU, DSP, GPU and a load of other things in the same die. They use a stacked-chip design so you can plug 128MB of RAM (256MB coming soon) on top of the package. Power usage is around 250mW.
How about a working variation of Hyperthreading?
Hyperthreading is a Intel's implementation of an idea that IBM brought to market first (based on an academic research project which produced the first prototypes, with the original designer now working at Sun). Sun and IBM have had it working for years. As have a few others. Unlikely in ARM chips, since the performance/power benefits in this space are worse than with multi-core (Cortex A9 allows up to 4 cores). It only makes sense for Intel in the Atom because it allows two context to share an instruction decoder, which reduces the cost of x86 bloat a bit.
How about hardware accelerated stacks?
x86 chips have had hardware accelerated stacks for well over a decade - rewrite an iterative algorithm with a software stack as a recursive implementation and you'll see a speedup.
MMUs that can handle a driver memory space
IOMMUs have been in Sun and IBM chips since they introduced 64-bit CPUs and wanted to plug in 32-bit PCI devices. Newer Intel and AMD designs also include them.
Advances in clockless processing?
Asynchronous designs have been floating around for a few decades but still don't deliver the kind of performance benefit that offsets the extra complexity (which equates to extra power usage).
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