100x Denser Chips Possible With Plasmonic Nanolithography

Roland Piquepaille writes "According to the semiconductor industry, maskless nanolithography is a flexible nanofabrication technique which suffers from low throughput. But now, engineers at the University of California at Berkeley have developed a new approach that involves 'flying' an array of plasmonic lenses just 20 nanometers above a rotating surface, it is possible to increase throughput by several orders of magnitude. The 'flying head' they've created looks like the stylus on the arm of an old-fashioned LP turntable. With this technique, the researchers were able to create line patterns only 80 nanometers wide at speeds up to 12 meters per second. The lead researcher said that by using 'this plasmonic nanolithography, we will be able to make current microprocessors more than 10 times smaller, but far more powerful' and that 'it could lead to ultra-high density disks that can hold 10 to 100 times more data than today's disks.'"

Comments

dense?

[chibiace]

what ever happened to smart chips?

5-10 years

[wjh31]

every great new technology is 5-10 years away i belive

Re:5-10 years

[Klaus_1250]

Except for nuclear fusion, that always 30 years away.

Re:5-10 years

[rubycodez]

very good news for you, electricity by fusion is no longer something promised 30 years away, now it's fifty.

Re:5-10 years

[Pantero Blanco]

And artificial intelligence. That's always 20 years away.

No, it starts off at 20 years away and gets closer, and once it's less than 5 or 10 years away, someone redefines it and it's back to 20.

Fragility

[Renraku]

A question for the physics people out there.

At what point does Brownian motion become a serious consideration? What about tunneling electrons and other quantum-ish effects?

Re:Fragility

[wjh31]

brownian motion isnt really relevant at this level, but i imagine that if the channel or 'wires' or whatever were close enough then tunneling could be an issue, but probability of tunneling falls off exponentially with the distance, and the severity depends on the energy, but if the wires are put close enough then it could be an issue, however only if there was just few atoms between channels

Re:Fragility

[mehtars]

Actually with processors using a 90 and 45 nanometer transistor size, there is a very high likely hood that a number of transistors will fail over the lifetime of the chip due to diffusion alone. Though modern processors have taken care of this by routing data through parts of the chip that are still active. Though this has an interesting affect of slowing the processor down as it gets older.

Re:Fragility

[Cyberax]

At about 5nm. Other effects should limit our current tech to about 10nm.

If "10 times smaller" is about chip area, then it might be possible - square root of 10 is about 3 and our current best lithography processes are about 30nm.

Re:Fragility

[Gibbs-Duhem]

Tunneling electrons and other quantum effects are already in effect in current devices. We just design around those effects instead of taking advantage of them currently. When we really get the ability to make reliable 5nm size scale parts, we'll just switch to quantum dot based transistors (single electron transistors).

Brownian motion isn't relevent here.

A big issue is that sharp features are thermodynamically unstable (lots of dangling surface bonds), so edges tend to "soften" over time due to surface diffusion. Also, at ohmic contacts you can get pits forming which can eventually degrade features.

Another issue is that at the size scales we're talking about, current insulators stop working. They're looking at switching to a variety of new materials for this purpose (for example, IrO2), but these are tricky. This is what they mean when they say "high dielectric constant" materials. Every MOS transistors has a this oxide layer (between the Metal and the Semiconductor), and that layer's thickness defines many of the physical properties of the device.

Finally, you have to worry about inductors to a lesser extent. Current inductors aren't quite good enough, but we're working on that too =) Nanoscale metallic alloys are definitely the way to go.

In any event, this article is sort of sensationalist (surprise!). I was able to make 20nm features using physical embossing (stamping metal liquid precursors with a plastic stamp and then curing them) back in 2002. Making features of small size scale is easy, it's keeping error rate, making interconnects, etc that's hard and annoying. Plasmonics is very neat though, I can imagine it working with time.

Besides, hard disks already have magnetic domains of ~ only a few nanometers anyway.

Re:Fragility

[ZarathustraDK]

A question for the physics people out there. At what point does Brownian motion become a serious consideration? What about tunneling electrons and other quantum-ish effects?

Depends on the fiber-content of the brownie...

Re:Fragility

[mehtars]

http://www.extremetech.com/article2/0,1697,1994121,00.asp
Here is an article on it. Although its from 2006, there has been more work done on it. There are more articles on it in the literature.
If you search for 'self healing' microprocessors you can find a number of articles on it.

That's good...

[kitsunewarlock]

These thin chips keep breaking off in my salsa.

Hooray for the Athlon64 X200!

[NerveGas]

Just think... we'll be able to have 198 cores doing nothing, now!

Plasmonic?

[gsgriffin]

Was this developed at the Gizmonic Institute?

Another maskless scanning lithography system

[Yarhj]

One of the difficulties with a scanning technology like this is throughput -- with mask-based lithography you can expose dice with great speed, while something like this will have to scan across the entire surface of the wafer. It sounds like there's good potential for parallelization (the article mentions packing ~100k of these lenses onto the floating head), so this technology won't necessarily be as slow as electron-beam lithography, but I can't imagine it'll be cheap either. Furthermore, the software and hardware involved must be much more complex than a conventional stepper; now you've got to modulate your light-source very rapidly, rotate your wafer, and keep track of the write-head's position to sub-nanometer precision. Tool design and maintenance costs will be pretty high, I imagine.

Re:Impact on Big chip manufacturers

[freddy_dreddy]

You have to make a difference between Fabs which produce ICs and companies that produce Fab equimpent. Off course they're intertwined but AMD and the likes is an architecture Co, where Companies like ASML drive Fab technology. The "slow rate" is set by industry agreements - milestones - to keep the cost of Fab tech R&D minimal. The shrink step is a factor 2 for surface, resulting in a factor sqrt(2) for feature size. Litho tech companies use this step because the market is not viable for developing Fab tech which takes a different approach: litho is just a fraction in the hundreds of steps it takes to produce an IC. If you were to implement a new Fab litho technique which differs from the roadmap you won't have customers because the technology isn't in sync with the other processes. In other words: this new technology is only viable if the others jump on the bandwagon, so far it's "only" proof of concept. The field of Fab tech R&D is filled with new concepts, but that's just a small part of the story.

Government funding

[philspear]

Nano-something you say? Can it possibly be used in the production of biofuels to increase homeland security against bioterrorism? If so I have a big check for you to pick up.

Re:Impact on Big chip manufacturers

[Valdrax]

Do current chip manufacturers like Intel and AMD work on new lithography techniques, or do they focus more on architectural changes?

Yes. This research was funded by the National Science Foundation, a federal agency, but IBM, Intel, and AMD are all active in process technology research. I can't dig up much in the way of what they're currently researching, but here are a few things I was aware of in the past few years (and some things I dug while looking for them):

• Intel was researching extreme-ultraviolet (EUV) lithography around 2002-2004.
• Intel is also funding research into computational lithography to avoid having to do immersion lithography, like IBM and others are doing for the next generation.
• AMD & IBM were partnering on a test fab for EUV lithography in 2006 and had successfully demonstrated the ability to create transistors but were still working on metal interconnects at that time. I'd bet money they've gotten past that point by now.
• IBM did a lot of pioneering work on strained silicon that they announced back in 2001.
• Silicon-on-insulator (SOI) was another fab technology they pioneered in 1998, but it hasn't spread much in the industry beyond them, AMD, and Motorola / Freescale -- in other words, IBM and its partners.
• And then again, back to IBM, they were the first company to come up with a viable process for laying down copper interconnects, using what's called a dual-damascene process, in the late 90's.
• Hitachi has been actively developing electron-beam lithography for over a decade, but the technology has yet to really live up to its promise as a commercially viable competitor for photolithography AFAIK.

Some of the above research was about commercializing "pure" research done in independent labs like this experiment, but a lot of it was directly funded by the big fabrication companies and their clients and partners. Since I'm not in the fabrication industry myself, I can't really comment any further on who has done what (and how much each of the above deserves credit). This is just news I remember from years past.

Space elevators

[Hal XP]

Don't forget the space elevator, which, according to the late Arthur C. Clarke will get built 50 years after it stops getting modded funny.