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Larrabee ISA Revealed
David Greene writes "Intel has released information on Larrabee's ISA. Far more than an instruction set for graphics, Larrabee's ISA provides x86 users with a vector architecture reminiscent of the top supercomputers of the late 1990s and early 2000s. '... Intel has also been applying additional transistors in a different way — by adding more cores. This approach has the great advantage that, given software that can parallelize across many such cores, performance can scale nearly linearly as more and more cores get packed onto chips in the future. Larrabee takes this approach to its logical conclusion, with lots of power-efficient in-order cores clocked at the power/performance sweet spot. Furthermore, these cores are optimized for running not single-threaded scalar code, but rather multiple threads of streaming vector code, with both the threads and the vector units further extending the benefits of parallelization.' Things are going to get interesting."
No, not at all.
If Indian coders are too stupid to bathe and use deodorant, their code won't go anywhere. This is sounding a lot like the Cyrix architecture in complexity. Parallelism is not that hard to deal with, but you have to know what you're doing and not stink like you knock buzzards of shit-wagons. Sadly, few do. Stinkies - try again in ten years.
Meanwhile, the few leftover American companies who are smart and un-Jewish enough to pay the extra 2 cents to hire whites will get code that works. Remember Windows Bangalore Edition a.k.a. Vista.
To answer my own post, I'm not entirely sure about some of the facts. Like,... if I like the musty smell of men, does that mean I'm gay?
Chase the moment. Where does it go? Exactly.
It makes me wonder why Apple was so quick to ditch the Power architecture and jump ship to x86. Intel really needs something other than x86 to compete with on the desktop end. I understand that the Power road map was stated to lose competitiveness with intel's offerings and all, but given the fabrication shortcomings it still appears to be very much in the race. It would be terrible to rely on one single chip manufacturer and it makes me happy that there remains quite a few different architectures out there. The potential is there for us to be on the verge of a quantum shift in computing and yet we still cling to dinosaurs that still boot into standard real mode like its 1981 all over again. Its interesting to see how badly the sparc is flailing on specint. It makes me wonder what IBM will do with the architecture when they acquire it. There is still a big rift on the RISC vs CISC debate and if modern chip designs show any indication, RISC as a concept still won by a long shot as it sits at the core of modern x86 cpus today.
From the wikipedia:
RISC and x86
However, despite many successes, RISC has made few inroads into the desktop PC and commodity server markets, where Intel's x86 platform remains the dominant processor architecture (Intel is facing increased competition from AMD, but even AMD's processors implement the x86 platform, or a 64-bit superset known as x86-64). There are three main reasons for this.
1. The very large base of proprietary PC applications are written for x86, whereas no RISC platform has a similar installed base, and this meant PC users were locked into the x86.
2. Although RISC was indeed able to scale up in performance quite quickly and cheaply, Intel took advantage of its large market by spending vast amounts of money on processor development. Intel could spend many times as much as any RISC manufacturer on improving low level design and manufacturing. The same could not be said about smaller firms like Cyrix and NexGen, but they realized that they could apply pipelined design philosophies and practices to the x86-architecture -- either directly as in the 6x86 and MII series, or indirectly (via extra decoding stages) as in Nx586 and AMD K5.
3. Later, more powerful processors such as Intel P6 and AMD K6 had similar RISC-like units that executed a stream of micro-operations generated from decoding stages that split most x86 instructions into several pieces. Today, these principles have been further refined and are used by modern x86 processors such as Intel Core 2 and AMD K8. The first available chip deploying such techniques was the NexGen Nx586, released in 1994 (while the AMD K5 was severely delayed and released in 1995).
While early RISC designs were significantly different than contemporary CISC designs, by 2000 the highest performing CPUs in the RISC line were almost indistinguishable from the highest performing CPUs in the CISC line.[10][11][12]
[edit] Diminishing benefits
Over time, improvements in chip fabrication techniques have improved performance exponentially, according to Moore's law, whereas architectural improvements have been comparatively small. Modern CISC implementations have adopted many of the performance improvements introduced by RISC, such as single-clock instructions. Compilers have also become more sophisticated, and are better able to exploit complex instructions on CISC architectures. The RISC-CISC distinction has blurred significantly in practice.
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