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Intel's Roadmap Includes 4nm Fab in 2022
Precision submits "Intel Corp., the largest maker of chips in the world, has outlined plans to make chips using 4nm process technology in about thirteen years. According to Intel, integration capacity of chips will increase much higher compared to fabrication process."
The next step of the plan: negative-sized chips by 2050!
Funny may not give karma, but +5 Informative never made anyone snort coffee out their nose.
These are long-term business forecasts for 10+ years down the line. They are thought experiments only, in my opinion. They are still valuable, and something to consider, but still very much a "projection" and not a "concrete plan with funding".
Just because I can hook a shark from a boat, I do no offer to wrestle it in the water.
They're looking at moving away from using silicon as a substrate. I can't remember if artificial diamond or something else is the proposed replacement.
I don't read AC A human right
Silicon's radius is 110 picometers which translates to .11 nanometers.
This is obviously pie-in-the-sky speak from the marketing dweebs, who don't understand the physical limitations that come with a die shrink.
"Intel Corp., the largest maker of chips in the world,
Is it really neccesary to explain who intel is on /.? I think even my parents know that intel makes chips, they put out enough commercials... Are even our taco overlords not really reading TFS before hitting that submit button?
http://greenobyl.com/ please.... think of the children!!
It just happens that my personal roadmap for 2022 includes a flying pony that craps gold. I'm cautiously optimistic.
By 2022, the only integrated circuits you'll have will be the ones you carve yourself, with your bare teeth, out of the bones of your children(during those rare times that you aren't fighting off hordes of monstrous rat-men or scavenging for survival in a grim Malthusian dystopia).
Except for the fact that a lot of the 'marketing dweebs' at tech companies are engineers.
Just sayin'. Your product management/marketing folks at these firms are often very plugged in to the tech side of things (I should know, being one of them).
I would suspect that unforeseen developments, such as big advances in 3d circuit design, would alter this schedule a lot. This is simply daydreaming.
Forget about the limitations of die shrink, what about the limitations of quantum mechanics? I was under the impression that 4 nm is getting awefully close to the point where quantum tunneling makes tansistors unworkable. As in, when you detect a signal, you can't tell if it's there because it should be or because an electron just jumped the gap.
Or...
Google claims that it's about 0.022 beard-seconds.
You are correct, they plan to transition from silicon to unobtainium.
If libertarians are so opposed to effective government, why don't they all move to Somalia?
The atomic radius is not the proper distance to consider. If you do so, you assume that atoms can touch each other, which is very far from the truth. The closest distance "allowed" is the first nearest-neighbor (NN), which is related to the crystal lattice constant (for Si: 0.543 nm), and the crystal structure (Si has a diamond structure). For Si that NN distance is 0.235 nm. This is all very much academic tough. Even if you could make a circuit that small, you would then have to wonder, left alone quantum-size effects, leakage, behavior under oxidation, etc.
It seems to me that rather than the identity and timeframe for the different technology nodes (which anyone who knows Moore's law could have given in advance) the interesting thing from that slide is what it says about delay scaling and energy scaling. Whenever you shrink your process you have a certain amount of gain that can go into either making the chip faster or making the chip more power efficient. For a long time back in the day people wanted to stay at 5 volts to preserve compatibility, so everyone just kept putting it into going faster. Nowadays chipmakers try to go for a more balanced strategy.
But here, on this chart, Intel is saying that they're going to a delay scaling of "~1", staying at pretty much the same speed. And they're looking to increase their energy scaling from "~.5" to ">.5". So it looks like we really have topped out in terms of GHz.
This sig wasn't worth reading, was it.
Here's a set of roadmaps generated at three-year intervals. Note that, with the exception of RAM density, each of the charted criteria outran the roadmaps' predictions.
These roadmaps are generated by a consortium of companies. They're routinely betting the future of their entire industry on these roadmaps. They're actually pretty darned conservative.
Hmm... 2013 can't be great for the gene pool. I guess it may be balanced out as 1/2 of the first generation's genes come from such an ambitious person.
:P
Or maybe
2014) Run out of lottery money on alimony payments
Interesting.
"After all there's a reason you're not actually working in enginerring, when you're such a great engineer..."
Yeah - the pay is better.
"As God is my witness, I thought turkeys could fly." A. Carlson
There have been formal semiconductor roadmaps to the future since 1992. There's an consensus roadmap updated annually by an industry group.
This isn't a blue-sky thing. It tells all the players what they need to do to keep up their part of the technology. The fab-equipment people, the device physics people, the etching people, the mask people, the substrate people, the design tools people, etc. all have to push their parts forward. The roadmap tells them how far each piece has to be pushed.
These roadmaps are available for past years, and you can see how the industry has tracked the roadmap. It's reasonably close for any five year period. The big change in the last decade is that heat dissipation is starting to dominate the problem. The roadmap now focuses on memory devices, which have low activity per cell compared to compute elements and aren't yet power-limited.
The current consensus is that the improvements to known technology can get down to 22nm, and then it gets hard. The roadmap assumes CMOS transistors; other devices are discussed, but aren't factored into the mainline predictions.
Except for a vial coated in an oil of slipperiness, if memory serves.
Interesting.