MIT's Hybrid Microchip To Overcome Silicon Size Barrier

schliz writes "MIT researchers have successfully embedded a gallium nitride layer onto silicon to create a hybrid microchip. The method could be further developed to combine other technologies such as spintronics and optoelectronics on a silicon chip. It is expected to be commercialized in a couple of years, and allow manufacturers to keep up with Moore's Law despite today's shrinking devices."

Comments

Self-fulfilling prophecy?

[Drakkenmensch]

It's been getting interesting these past couple of years to see chip manufacturers not only content with observing the results of Moore's Law, but working hard to actually meet it as a self-imposed deadline. Would Intel have come as far as it did recently if Moore had never put his famous observation onto paper?

Re:Self-fulfilling prophecy?

[TheRaven64]

Would Intel have come as far as it did recently if Moore had never put his famous observation onto paper?

Yes. Someone else would have made a similar guess. Developing a CPU takes around 5 years. When you start, you need to know roughly how many transistors you will be able to use to make it. This depends on the market segment it will be aiming for (and the amount people are willing to pay for a chip in that segment) and the number of transistors you will be able to fit on a chip for that much money. Moore's 'law' is a good rule of thumb that lets you make a reasonable guess as to how many transistors you can fit on a chip by the time it is ready to be made. Sometimes it works, sometimes (e.g. the P4) it doesn't. Without it, Intel would have had to use some other mechanism for making guesses, but given that Moore's law is just a simple extrapolation from their past performance, that's probably what they would have used anyway.

Re:Does Moore's Law end when things get too tiny?

[jeffb (2.718)]

Smaller equals faster, and can equal lower power. Both of these are good for cellphones, and lots of other things.

More to the point, this particular advance means fewer individual chips, which means cheaper.

Re:Beowulf

[Drakkenmensch]

Imagine a Beowulf cluster of those... in my smartphone.

Eventually the smartchip in your credit card will get bored, nano-build a wifi connector out of the card's polymers and connect to the net, building its own Facebook page and getting more friends than you have. And then Skynet wins teh interwebs.

Great idea

[AP31R0N]

i should get my girlfriend to use silicon to overcome her size barrier.

Not what Moore's Law means

[imgod2u]

They aren't talking about shrinking existing MOS transistors (which make up 99.999% of digital circuits); which is what Moore's Law talks about. They're talking about the ability to integrate transistors with better matching characteristics (CMOS is terrible at it) for analog and photoelectric circuits onto existing silicon. This idea has been done again and again from Intel's hybrid silicon laser to Silicon Germanium, which is already widely used in cell phone chips.

This won't make digital circuits smaller and isn't a solution to it so the headline isn't accurate. What this will mean is that potentially, cell phones won't need 4-5 separate chips for RF, digital, baseband, etc. You can integrate all those functions into one. But again, that's nothing new. IBM already provides BiCMOS with a SiGe layer on top for analog circuits. It's not been economical since it usually lags behind their bulk CMOS process for digital-only chips.

Re:Hybrid microchip

[Fred_A]

MIT researchers have successfully embedded a gallium nitride layer onto silicon to create a hybrid microchip.

Arthur: What do you mean, an african or european gallium nitride layer?
Bridgekeeper: Both! That's why it's an hybrid!
Arthur: I didn't know that! Auuuuuuuugh!

Meanwhile, a few hundred years later...

Customer : So, um, I'll only have to refill my computer half as often right ?
Best Buy Salesperson : Actually it so happens that we have a promotion on computer tanks in the next aisle.

Re:Does Moore's Law end when things get too tiny?

[imgod2u]

You're talking about coupling capacitance, which is something that can be alleviated by design. The biggest issue is that shrinking wires don't result in faster signals due to the load capacitance remaining relatively the same. This becomes the majority of the delay and the speed of the transistor becomes a smaller part of the equation.

Add to this the fact that transistors themselves aren't getting faster. The speed of a FET is proportional to its gate dielectric thickness. That is 1nm at 45nm and 0.9nm at 32 (for Intel). This can't really shrink much more like it has in the past -- once you're down to a single layer of Hafnium, you can't really cut out any more -- and as a consequence, transistors won't be getting faster at the same rate that they have been in the past (for MOS at least).

Looking at Intel's roadmap, upcoming node shrinks scale in power and size but not in speed.

On "exponential" growth

[sean.peters]

Technology often makes other technology easier, so you have an exponential chain reaction.

I hear a lot about the "exponential" growth of technology. I'm not sure whether technology is really growing exponentially, but I do know this: exponentially growing processes don't go on forever - they can't. Rather quickly, they hit upon some underlying limitation in the physical world, and progress stops. I think it's much more likely that growth in technology follows a logistic curve, which grows pseudo-exponentially for a while, but then plateaus. We're just in the steep part of the curve right now.