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Intel Allows Release of Full 4004 Chip-Set Details
mcpublic writes "When a small team of reverse engineers receives the blessing of a big corporate legal department, it is cause for celebration. For the 38th anniversary of Intel's groundbreaking 4004 microprocessor, the company is allowing us to release new details of their historic MCS-4 chip family announced on November 15, 1971. For the first time, the complete set of schematics and artwork for the 4001 ROM, 4002 RAM, 4003 I/O Expander, and 4004 Microprocessor is available to teachers, students, historians, and other non-commercial users. To their credit, the Intel Corporate Archives gave us access to the original 4004 schematics, along with the 4002, 4003, and 4004 mask proofs, but the rest of the schematics and the elusive 4001 masks were lost until just weeks ago when Lajos Kintli finished reverse-engineering the 4001 ROM from photomicrographs and improving the circuit-extraction software that helped him draw and verify the missing schematics. His interactive software can simulate an ensemble of 400x chips, and even lets you trace a wire or click on a transistor in the chip artwork window and see exactly where it is on the circuit diagram (and vice-versa)."
When we get the Core i7 details, will it seem as quaint as the 4004 does now?
Link: http://www.youtube.com/watch?v=j00AULJLCNo
Here be signatures
It'd be nice to remember that the Italian Business was a good thing in this case at least!
Maybe Computers will never be as intelligent as Humans.
For sure they won't ever become so stupid. [VR-1988]
Real chips were made up at some point. Computer architecture classes should teach you the concepts, then when you go work for Intel you can find out all about the latest secret architectures, and you can apply what you learned in CA to making them better. Obviously you can't expect Intel to give out schematics for Core i7's or they would quickly go out of business.
Unfortunately the Intel 4004 is much less sophisticated than even the simplistic models I studied as an undergrad. Not to mention that real chips suffer from real compromises and real problems, something our academic fantasy-land models never had to deal with. The simple models allow the students to learn the important concepts (such as multi-cycle instructions, pipelining, caching) without having to worry about why it was implemented a certain way, the concepts are what counted.
In my computer architecture classes we at least looked at the IA32 architecture but it was more of a space-filler and not a primary focus, our professor was heavily into MIPS.
I guess I'm wrong. They crammed 45 instructions into the architecture using instruction words of varying width.
...run Linux?
j/k
This should actually be quite cool. I can see garage-based tinkerers messing with this chip, the registry and even coming up with a retro User Group.
The Kai's Semi-Updated Website Thingy
4004 - chip not found.
For the most part - Newer digital designs are language driven, not schematic driven. The advent of Verilog & VHDL lead to purely digital designs done up in code.
Some of the special devices are done using transistor level design, but synchronous logic these days is a HDL (hardware description language) followed by gate level synthesis, and then autoplace and auto routing.
A lot of fine tuning along the way for high performance items does get tweaked a lot but for the most part, digital chips are created as a coding exercise.
www.effectiveelectrons.com "chips that work" Analog, RF, Mixed Signal
*repeats a mantra* I will not feed the trolls, I will not feed the trolls....
Linux is Software. And Red Hat doesn't sell the software, they sell support contracts for the software. You can get RedHat's distribution for free through CentOS and are only paying for technical support and the nice pretty RedHat-specific graphics when you buy RHEL. Nobody is going to make money giving away modern chip designs for anybody else out there to manufacture, because there's no way for them to get an ROI on the development of said architecture. CPU's very rarely need tech. support, and aside from hardware design quirks (which coders simply code around), the only time you have a technical problem with a CPU is when the manufacture is defective and you need to replace the chip.
The closest anybody in the chip design sector ever comes to what you're advocating is ARM, and they don't give anything away. They design and test, and then license the manufacturing out to 3rd parties. They also vigorously enforce their licensing contracts and copyrights, because people paying them royalties for the use of their designs is the only way that they can make money.
Fuck. I will not feed the trolls again. I will not feed the trolls again....
I just found it ... it was in my programmable calculator from high school (EC-4004 from Radio Shack). Still works too.
better question, how would they physically handle a processor that small, 4004 has 2300 transistors, http://en.wikipedia.org/wiki/Intel_4004 , and the i7 has 731 million transistors at 45nm at 263 mm^2, http://www.legitreviews.com/article/824/1/ , So by those numbers the 4004 on a 45 nm process would have an area of .00082749 mm^2 or 1/317826th the physical size of an i7 die. Disclaimer: this is a very rough calculation, but in any case it is more than 5 orders of magnitude smaller than an i7. On the other hand you could have the king of multicore processors....
http://www.intel4004.com/ goes into much greater detail about Federico Faggin (primary co-developer and project leader), and the story of his accomplishments before and at Intel, his physical signature on all 4000 series chips, Intel's successful attempt to discredit him and patent his invention (the buried gate) that he invented at Fairchild before coming to Intel, and his departure to found Zilog with some members of his older design team.
Intel has been playing their game their way for a very long time.
In the very early 70s our engineering group was interested in using the new 4004 to simplify the production of control systems for heavy machinery (windlasses, hydraulic systems, etc). The machinery itself was slightly different from contract to contract and even from item to item within a contract so we had to design a new control system for each unit. When the 4004 came out we were excited to see if we couldn't do it cheaper and faster using a microprocessor.
We had moved from relays and discrete wiring to CMOS components on printed circuit boards and thought that was a big step. CMOS could be run at 15vdc which meant that the noise inherent in the environments our machinery worked in would not be quite as big a problem.
Unfortunately we discovered that we had several problems including the limited instruction set and memory capabilities of the 4004 along with the lower voltages needed so we stuck to CMOS until I left a couple of years later.
Still, the 4004 was my introduction to microprocessors and that changed the course of my career from electronics and electronic control systems to digital control systems and computers.
It's been an exciting ride, too. I am grateful to have grown up with the technology.
No one ever had to evacuate a city because the solar panels broke!
Probably the same 740kHz that the original 4004 had.
The manufacturing process used has nothing to do with the maximum clock speed a chip can achieve. It's about energy bleeding (heat loss) and the transistor density. If you manufacture a 4004 using 1950's-era technology, with actual honest-to-goodness 1mm-thick copper wire and large physical transistor switches, it'd be a *lot* bigger, but it'd achieve the same 740kHz that the design allows for.
The reason using a smaller manufacturing process translates into a higher clock speed is that the smaller manufacturing process means that each logic gate takes up a smaller amount of space on the die. This means that you can cram more transistors in to the same area of silicon, allowing you to complete more operations per clock cycle. This way, using a 40nm process instead of the original manufacturing process means that you can build a 4004 that takes up a ridiculously small amount of physical space, not that you can magically build one that's faster than the original design. :)
One of the things I hated most about my computer arch class was that we had to learn about a completely made up system design which didn't translate to ANYTHING in the real world. Oh yeah, and it was RISC. *Snoooreeee*
That's only because you dropped out before getting to the FPGA classes!
Any functional CPU design (technically non-functional ones too, for whatever good that would do) can be flashed into an FPGA and become as real as any other silicon chip.
And identical to psudocode, psudo-chipfab can be translated into any real code/fab language by anyone that knows basic design and the target language. You were supposed to be learning the basic design part, so once you got to using a real language used in the real world, you would have some clue what to do with it.
This means that you can cram more transistors in to the same area of silicon, allowing you to complete more operations per clock cycle.
This is true, but smaller process nodes also produce faster transistors. When you make things on the chip smaller, you have the practical effect of reducing parasitic capacitance in transistors and interconnect. Lower capacitance means a smaller RC time constant (using a first-order model), so logic will work faster. Intel's 45nm process can create an inverter with a delay of less than 5 ps.
Your statements imply that transistors have a fixed speed, and that the only way to improve performance is parallelism. This is false.
> If the Core i7 schematics were released, any old fab company could start making their own i7's for next to nothing.
Wrong.
Let's even imagine for the moment that you really meant that they'd release the verilog/vhdl, instead of schematics. There are still a few minor problems in the way:
1 - Intel really does have absolutely top-notch processing capability. Typically their top-end CPU pushes their top-end process for all it's worth, both in performance and capacity. (I'll add the caveat that "all it's worth" is a moving bar, which is why speed bumps and die shrinks come along as a process and design mature.) Chances are most fabs in the world simply won't be able to handle the Core i7 - not enough transistors.
2 - Let's pretend that you have a fab that can put out bigger-than-postage-stamp sized chips, and they can handle the sheer number of transistors. Most likely you still can't hand over such HDL, push a button, and have a layout come out, even bigger and slower. For one thing, a significant fraction of those transistors are in cache - probably SRAM. HDL doesn't build SRAM, it instantiates it. You need either a compiler or an SRAM design team(s) to get the cache(s) built, and they have to be specifically matched to the interface the HDL is expecting - these aren't garden-variety commodity SRAMs, by any means.
3 - So let's pretend we have SRAMs too, and that the design we had in our back pocket could be tweaked to meet the interface requirements of the Core i7. We have datapath/dataflow problems. In the first place, those datapaths are highly regular - kind of like bit-slices. A lot like bit slices, in fact. Most likely the design was carefully partitioned into functional blocks, and those functional blocks were further partitioned, etc. Then they were floorplanned with an eye to the final design. Far from the smallest concern was getting all of those bits from point-A to point-B to point-C. These things have some pretty big buses inside, and just about everything is high-performance.
In short, a schematic, even verilog/vhdl is a far cry from the whole picture. Even in today's push-button world, you don't push-button a thing like the Core i7, or even latest-generation AMD CPUs, to be fair. You need to have a talented, experienced physical design team, and there's as much work there, maybe more, than simply coming up with the logical design. Then again, frequently the logical and physical design may not be that separated - a really tight feedback loop between the two can work well.
So go back to your super-sized non-optimized chip done with push-button tools - oh and by the way, you may have a hard time finding such tools with enough capacity. The resulting chip won't be a little bigger and a little slower - it'll be a LOT bigger and a LOT slower.
Does anyone know what the technology was for the 4004? (Is that metal-gate, with double-metal, or polysilicon gate with single-poly, single-metal?)
The living have better things to do than to continue hating the dead.
Available for non commercial use? Are they even entertaining the possibility that somoent might try to profit from the design?
SJW n. One who posts facts.
I have an original hardcopy Intel 4004 User's Guide I nabbed from the 1970 Wescon exhibition. Reading through that - butterflies. Yes, the quantum weather software butterfly would have been an easier IDE.
Do not mock my vision of impractical footwear
Does anyone know what the technology was for the 4004? (Is that metal-gate, with double-metal, or polysilicon gate with single-poly, single-metal?)
Well, I do look at photomask stacks as part of my job from time to time as a process integration engineer (mask bugs do make it past design rule checking and tapeout sometimes) but I will start with a disclaimer that this chip and process was designed before I was alive.
It looks from the composite drawing that this is a single poly/single metal/self aligned doped poly/source/drain. That should have existed at the time and to my knowledge no metal gate process has been in wide use because of manufacturability and performance problems. It looks like the red is poly (gates and lines), blue metal, and the green is the source/drain/poly doping diffusion. Whether that was done with implantation or glass doping I'm not sure (again before my time, implant was coming into use but glass doping was much cheaper, if not as controllable). It is kind of nice to see such a simple design.