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8-Core Intel Nehalem-EX To Launch This Month
MojoKid writes "What could you do with 8 physical cores of CPU processing power? Intel's upcoming 8-core Nehalem-EX is launching later this month, according to Intel Xeon Platform Director Shannon Poulin. The announcement puts to rest rumors that the 8-core part might be delayed, and makes good on a promise Intel made last year when the chip maker said it would release the chip in the first half of 2010. To quickly recap, Nehalem-EX boasts an extensive feature-set, including up to 8 cores per processor, up to 16 threads per processor with Intel Hyper-threading, scalability up to eight sockets via Intel's serial Quick Path Interconnect and more with third-party node controllers, and 24MB of shared cache."
Given that the Nehalems all have integrated memory controllers, I'd assume that the memory I/O situation wouldn't become substantially worse as you scaled up.
From TFS's mention of "up to 8 CPUs or more with third-party node controllers" I'm(perhaps optimistically) assuming that that means all the RAM in an up to 8 socket system wouldn't be more than one hop away from any core.
They almost certainly didn't go with 24MB of cache because their main memory situation is perfect; but intel's bigger chips are substantially improved from the old "Hey, let's hang a bunch of super expensive Xeons off a dubiously adequate northbridge through a shared front-side bus, let them starve for memory access, and then get curb stomped by cheaper Opterons!" days.
I'm thinking computing power for rent (aka the cloud), VDI, cluster data crunching , and any combination of the above
So can we now expect a doubling of cores every 18 months?
Even funnier, soon enough you'll be running Crysis on your cell phone (or whatever we call it then). Remember when it was tough to get decent framerate on Doom with high settings? You can run that on a cellphone these days. 15 years from "state of the art" to "runs on my cellphone." Wow. In 15 years you might have a 1TB database running on your personal communicator that fits in your pocket. (in keeping with the "15 years out" prediction theme of the day.
This makes me sad. Web 2-point-Oh is such a waste of a perfectly good 8-core processor.
10 years ago if you had told me about an 8-core processor I would have imagined using it for kick-of-the-ass games, immersive virtual reality, editing 3D video and simulating newer, more deadly designs of chainsaw chain.
But noo, instead they are used to pump out inefficient JavaShit-based versions of the Desktop software we had in '93 with a shiny new rounded corner interface to web browsers around the world. Great.
Yea, it really bugs me how 95% of a web site's load time and processing load is accounted for by a few pretty features like rounded corners and drop shadows.
How about we put those effects into CSS where they below and not induce massive load by simulating them with 5mb of JavaScript?
I hate printers.
People have been arguing as you are that x86's bloated CISC instruction set was inferior to a cleaner RISC architecture for the last 20+ years. Nobody has ever proven that the elegance of the instruction set matters with hard data though.
What evidence we do have goes against that argument.
The only evidence that we have is that the benefits of commoditization and economies of scale often outweigh any architectural advantages. The fact that x86 incorporated many elements of RISC would also demonstrate its value.
Apple machines used a cleaner RISC architecture for a while in the desktop space. They never performed any better than equivalent x86 based machines, and in the end Apple abandoned RISC and moved to x86.
Manufacturing processes simply trumped architectural differences. PowerPC's have never been manufactured on anywhere near the scale of x86.
Intel came out with a cleaner RISC based instruction set that that the Itanium line uses. If x86 was really as bad as you say, Itanium chips would be running circles around the x86 based server chips provided by both Intel and AMD. That isn't happenning.
Itanium is EPIC, not CISC. It is the exact opposite of RISC. It may not be running circles around x86, but that may be due to compilers not yet being advanced enough to take full advantage of the architecture. We may still see this change in the future.
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