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Can Transistors Be Made To Work When They're Off?
An anonymous reader writes "Engineers at the Belgian research institute IMEC are looking at the use of silicon transistors in the sub-threshold region of their operation as a way of pursuing ultra-low power goals. A chip the engineers are designing for biomedical applications could have blocks designed to operate at 0.2 or 0.3 volts, researchers said, according to EE Times. The threshold voltage is the point at which the transistor nominally switches off. Operating a transistor when it is 'off' would make use of the leakage conduction that is normally seen as wasted energy, according to the article."
Cool! So... what does that mean?
I believe that if you were to try and utilize the leakage current, it would only cause that much more resistance, making it require more current to stay "off". This would be a good way to get a government grant in publishing some R&D for this, but in reality, I imagine that the amount of complexity that this would add to a device would outweigh any benefits. Plus, most transistors that just sit there in the off state are off because the entire device is off and doesn't require any current. The energy put into thinking about this would far outweigh any perceived benefits.
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I heard about this research topic over a year ago when I took VLSI. The main problem, as I understand it, is not building circuits that operate below the threshold voltage, but actually reading the output of those circuits.
Palm trees and 8
I know when I'm off theres no chance of me workin...
As we've scaled deep into the submicron region, it's been getting harder and harder to turn the devices really "off". Leakage current has been rising and has been quite noticable for several generations now.
So the idea of doing useful work with subthreshold current sounds neat
(OK, I just went and read TFA.)
Still sounds neat, but...
In deep submicron part of the reason for the subthreshold leakage problems is control of Leff. (The effective channel length of the FETs.) There's a thing called "line length variation" which means that channel lengths in different parts of the chip will be different, sometimes subtly, sometimes not so subtly. Threshold voltage (Vt) is a strong function of channel length, making subthreshold leakage also a strong function of channel length. Performance characteristics will vary widely across the chip, likely much more than conventional transistor operation.
This will make it tough to scale down, (in feature size) scale up, (in chip size) and make manufacturable.
The living have better things to do than to continue hating the dead.
Notable among those applications are ... wristwatch chips. Eric Vittoz has made a career of this mode of operation. You can't set foot in the subject without running across patents, books, articles -- Hell, probably recipes by him going back 40 years.
Lacking <sarcasm> tags,
Germanium transistors predate silicon and have just as low a voltage drop and have a high leakage current.
The thing that popped into my mind while reading this was the possibility of this being used to operate the entire system at this level (rather than just making use of leakage). If it could perform fast enough, this could potentially massively reduce power consumption, and thus the need for cooling as well.
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A male genitalia heat extraction device. Power devices and increase the dismally low western world sperm count in one.
Not patented yet because I don't know how to make one. Someone do it!
Sounds awesome. Good luck scientists!
Another commenter is correct in pointing out that what they're doing is using leakage current. When we measure power dissipation, we count two things, (a) dynamic power, which is used when a transistor switches and is a function of frequency, voltage, and temperature, and (b) static (leakage) power, which is always going on and is a function of voltage and temperature. At 180nm, the ratio of dynamic to static was about 1000:1. It started to become noticed at around 90nm and a problem at 65nm. Now at 45nm and 32nm, leakage is about half the total power usage. The best way to lower power is to reduce voltage, but this kills performance scaling. Scaling down transistors reduces dynamic power but increases relative static power, which is why processors like the Core i7 use not just clock gating but POWER gating, dynamically, at a functional unit level.
Regarding subthreshold, as you lower voltage, power goes down. The problem is that transistors also get slower. Above threshold, the power goes down faster than speed, so if you're using a transistor with threshold voltage of 150mV with a supply voltage of 300mV, you get like a 100th the power dissipation, but a tenth the speed, which means that you use one tenth the energy to perform some process. As you lower the supply voltage below threshold, the transistors get slower faster than the power goes down, so total energy actually goes up as you lower voltage below a certain point. There is a supply voltage point either side of the threshold voltage where energy is minimum for the range. You use near threshold or sub threshold depending on if you care about speed. Also, things behave quite differently at low voltages, so you have to change all your design techniques.
One of the problems with near and sub threshold is that you don't actually know what your threshold voltages are anymore. It's called process variation. The transistors are so tiny that you get on the order of tens of dopant atoms per transistor. The doping process is highly random, so you get wide variance on threshold voltage (and effective channel length too), meaning that two transistors next to each other have different switching characteristics. This is actually a major problem at 32nm, resulting in unfortunately large supply voltage margins to avoid timing-related errors, which translates into excessive power usage. It's an even bigger problem when the supply is near the threshold (above or below), because the speed of a transistor and its power output are actually functions of the difference between supply voltage and threshold voltage. If the supply is 300mV, then the transistor with Vth=130 is going to be way faster (and way leakier) than the transistor on the same die with Vth=170. Of course, both were designed to have Vth=150, but you can't control that well enough.
My area of research involves coping with the 5X decrease in reliability at NTC, and I'll talk more about it when my papers are accepted. :)
As far as I know (i.e., according to some professors I've spoken to), transistors in devices with extremely long battery lives, such as hearing aids and watches, are typically operated in sub-threshold in order to conserve power. Of course, these devices are also typically not speed-critical. A lot of biomedical applications probably fall under the umbrella of requiring low power (for battery life and/or thermal reasons) and not requiring high speed, making the application a natural fit for sub-threshold operation.
Using transistors in sub threshold modes has been around for ages. Carver Mead proposed their use for modeling neurons in silicon ages ago and there have been others who use these techniques for other low power techniques. See Delbruck(Zurich ETH) or Boahen(Stanford/Penn) or Andreou(Johns Hopkins). Two of my undergrad profs did thesis work at Georgia Tech using these techniques as well to do neuromorphic engineering tasks.
I don't care what you say, all I need is my Wumpabet soup.
This is nothing new, this behavior of the CMOS transistors in the subthreshold region of operation has been known for years. I actually wrote a paper 5 years ago on a circuit using transistors in the subthreshold mode of operation. As always, there are trade-offs, and the main one is that the frequency of operation is a lot lower than if the transistor would have worked in the normal region. The main advantages of running the transistors in this operating region are low power and the fact that the current vs. voltage law changes from the quadratic law in the regular operating region, to exponential here, i.e. I ~= e^[n(VGS-VT)/kT] (see Sedra&Smith's or any other reference electronics book). So don't dream of your next low power processor using this technology. This is more suited for analog applications (one of the first ones that I remember is current multipliers and low-power current-mode analog circuits) and this is how these guys at IMEC seem to be actually using it.
RF and Audio circuitry has always used transistors in the cut off state. Detectors, class B, C amps, etc are examples. Most of what I know about is analog which is mostly history. There probably are applications that could utilize this technology however, as I remember the cut off region was very non-linear and work great for detectors. Maybe you could make a quad core cut-off processor that works great as an am radio detector!
Mod parent UP!!!
"Off and off-er" or "off and almost-as-off"?
Reminds me of - It depends on what the definition of the word 'is' is
Which of course leads to the arch typical;
"When I use a word," Humpty Dumpty said in rather a scornful tone, "it means just what I choose it to mean -- neither more nor less."
This issue is a bit more complicated than you think.
Forget the P = NP question - does PNP = NPN?
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Funny, but I was just reading an old radio magazine, circa 1938, where they were using 5 to 6 volts to the heater of a rectifier tube that usually needed 25. That's 1/4 the voltage, about 1/16th the power, and the rectifier worked BETTER at detecting radio signals than at full voltage. Some complex thing about the diode work functions one might suspect.
Engineers have explored most corners of the performance envelope, nothing all that new under the sun.
The current into the base of a bipolar transistor has a logarithmic relationship to the BE voltage. That means it is only really off when the base voltage is exactly zero. This makes the article title BS.
Most ACs are not even worth the keystrokes to insult them. Be generically insulted by this and ignored otherwise.
The goal of low power transistors is reasonable, but a new transistor design may be needed. The brain can do a lot of operations with little power but in terms of clock speed, the brain isn't that fast. A similar design may be good for low power electronic decisions - massive number of circuits at low frequency.
Know your pads. One time pad: good for cryptography. Two timing pad: where to take your mistress.
No.
This technique will probably require much tighter control over some figures of merit (specs) that are traditionally not that tightly controlled. For example, junction capacitance and resistance, as well as the thickness of the junctions themselves, will have to be elevated to a level of process-control precision that will likely make this a laboratory curiosity for a while.
Just to Chime in with Everyone saying this is old, I work with a professor who does subthreshold digital circuit design almost exclusively as his area of research. I'm an undergrad, but I read a paper by one of his grad students recently, the guy designed an FPGA that operates entirely in subthreshold. Just google it, you'll find stuff.
You would be closer to say PNP = -NPN. Especially if you carefully define the - operator.
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Sarpeshkar has been doing this for a while now. He teaches a good class on it:
http://www.rle.mit.edu/avbs/schedule.html
This isn't really anything new. Sub-threshold circuits have been being researched (and built!) for several years. I had some experience with them in some graduate courses I took when I was finishing up my undergraduate EE/CPE degrees last year. They actually are not that much more complicated than traditional CMOS, and the circuits basically end up looking the same (at least inverters, NAND's, etc.).
Since you are dealing with much less charge per unit time, it just takes a lot longer for the devices to operate. Since power consumption (switching power) is related to voltage in CMOS circuits as V^4 (that's not a typo, and I'm not talking about P=IV), sub threshold circuits allow for extremely low power consumption for the albeit slow speeds that they operate at.
When you think about sub VT circuits and the technologies that we work with now (like 32nm), the uses for this technology are profound. I know that at my alma mater there was lots of research into using sub VT technology for chips embedded into your body and for sensor networks. These chips require so little power that there was lots of talk and research about using energy that your body produces like heat to power these devices instead of relying on batteries which need to be replaced. Pretty cool stuff, in my opinion.
This is not new, Carver Mead first proposed this many years ago it is been used to develop micro power VLSI circuits. The main problem is the transfer function of the active region is not linear but exponential. This creates some interesting problems for traditional transistor design. Look up neuromorphic engineering for further reading.
Just remember, P = NP for sufficiently exotic definitions of '='