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Engineers Create Tiny Wires WIth Old Technique
Gamp writes with this interesting snippet: "As microprocessors have shrunk, the wiring between them hasn't always kept up. But engineers at the University of Illinois are changing that with a decades-old metalworking technique. It's called electrodeposition. It's basically the same process used in electroplating, but instead of depositing metal on a surface, as when trying to make a gold-plated piece of jewelry, the metal is deposited in a wire. 'People weren't thinking about how to fabricate a wire in three dimensional space,' said Min-Feng Yu, a professor of mechanical science and engineering."
I hate it when news articles don't either link to the original scientific paper, or at the very least tell me what issue of what journal it was published in! Given the state of journalism-about-scientific-research, I like checking up on the original paper, either for more details, or for a better "related work" section (often the actual papers will be much more honest than the press releases about which parts of the work are new and which parts aren't, and how it relates to existing work).
Anyway, it's this:
Jie Hu and Min-Feng Yu (2010). Meniscus-Confined Three-Dimensional Electrodeposition for Direct Writing of Wire Bonds. Science 329(5989): 313-316.
10 PRINT CHR$(205.5+RND(1)); : GOTO 10
Any impact on Moore's Law?
Well, according to TFA:
Scaled up to industrial size, the method could save microprocessor companies a lot of money, Yu said, because about 30% of the space in a microchip wafer is taken up by the wires between components
Given that, I'm going to tentatively answer your question with a "yes."
Technically a bit different issue than the way Moore phrased it, but conceptually could have some related effects. Moore was predicting an increase in transistor density of integrated circuits (ICs), while this work scales down the size of interconnects between separate ICs. That could have the same effect of increasing overall transistor density for an electronic component, but is a somewhat different than increasing transistor density within a single IC. For example, it won't allow CPUs to pack transistors more densely, because CPUs are already a single IC.
10 PRINT CHR$(205.5+RND(1)); : GOTO 10
For anyone interested in seeing what the results of this technique create, check out the NewScientist article that covers the same topic:
http://www.newscientist.com/article/dn19181-growyourown-approach-to-wiring-3d-chips.html
Oh IC now.
It could be more tightly related than that, but it depends on how scalable and reliable it is. Rather than predicting an increase in transistor density, Moore actually predicted an increase in transistor density at a fixed price-point. This is the same as a reducing price-point for a given transistor budget.
So one way to increase power would be to assemble processors out of smaller units. If each unit is an IC with a fixed transistor budget and this provides a reliable and scalable way to assemble those ICs into chips then it could have quite a large impact on the growth of processor performance.
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As someone actually deep in the industry (rather than speculators and wannabes), specifically to density and Moore's Law, I'd say not so much. Reason: electromigration. It's electromigration that defines design rule line widths for metal in microelectronics.
The researcher (like most/many academics) is clueless about real life applications and doesn't really understand the driving factors of the technology he claims this could replace. I.e. he's pulling masturbatory fantasies out of his ass when he talks about that 30% improvement. That's the problem with specialization and with ivory tower isolation.
Electromigration is the failure mechanism of very small metal lines and wires in microelectronics. Basically momentum of electrons in a current is transferred to metal atoms and they are forced to move. This results in extrusions and voids in the metal line forming over time. The effect occurs to some degree over time at all temperatures and all currents - only the rate of action is changed. Because voids increase resistance and thus current density, the system has a positive feedback loop.
Making lines smaller raises the current density which raises both the electron flux and the temperature of the metal line which both increase electromigration. It doesn't really matter what technique (to 1st order) you use to make the line; making the lines smaller is the critical 1st order factor affecting failure rates.
If (and only if) this technique can impact the grain boundary orientation could the reliability be improved but even then current thin film deposition techniques mostly have this dialed in already.
The place I see this having the most value is in being able to create entirely new wiring schemes such as 3D integration or in planarizing things like wire bonding to get the photolithography advantage. The latter less so - planar alternatives already exist. That's about it.