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How Much Smaller Can Chips Go?
nk497 writes "To see one of the 32nm transistors on an Intel chip, you would need to enlarge the processor to beyond the size of a house. Such extreme scales have led some to wonder how much smaller Intel can take things and how long Moore's law will hold out. While Intel has overcome issues such as leaky gates, it faces new challenges. For the 22nm process, Intel faces the problem of 'dark silicon,' where the chip doesn't have enough power available to take advantage of all those transistors. Using the power budget of a 45nm chip, if the processor remains the same size only a quarter of the silicon is exploitable at 22nm, and only a tenth is usable at 11nm. There's also the issue of manufacturing. Today's chips are printed using deep ultraviolet lithography, but it's almost reached the point where it's physically impossible to print lines any thinner. Diffraction means the lines become blurred and fuzzy as the manufacturing processes become smaller, potentially causing transistors to fail. By the time 16nm chips arrive, manufacturers will have to move to extreme ultraviolet lithography — which Intel has spent 13 years and hundreds of millions trying to develop, without success."
This is also why Intel has been investing so much into in-silicon optical interconnects. They can go 3D if they can separate the wafers far enough to put a heat pipe in between and still pass data.
Since they are so parallel they are made as a bunch of blocks. A modern GPU might be, say, 16 blocks each with a certain number of shaders, ROPs, TMUs, and so on. When they are ready, they get tested. If a unit fails, it can be burned off the chip or disabled in firmware, and the unit can be sold as a lesser card. So the top card has all 16 blocks, the step down has 15 or 14 or something. Helps deal with cases were there's a defect, but overall the thing works.
What are you talking about? AM2 boards support AM3 chips.
You also present a false dichotomy, because upgrading isnt ONLY about buying suboptimal hardware and then upgrading it later. Anyone who purchased bleeding edge AM2 gear when it was introduced can get a bios update and then socket an AM3 Phenom II chip. They still only have DDR2, but amazingly Phenom II's support both DDR2 on AM2 and DDR3 on AM3.
So that guy who purchased a dual-core AM2 Phenom when they were cutting edge can now socket a hexa-core AM3 Phenom II.
Its amazing what designing for the future gives your customers. Intel users have only rarely had the chance to substantially upgrade CPU's.
"His name was James Damore."
Because nowadays, the ISA is really very little impact on resulting performance. The total die space devoted to translating x86 instructions on a modern Nehalem is tiny compared to the rest of the chip. The only time the ISA decode logic matters if for very low power chips (smartphones). This is part of the reason why ARM is so far ahead of Intel's x86 offerings in that area.
Modern x86, with SSE and x86-64, is actually not that bad of an ISA and there aren't too many ugly workarounds necessary anymore that justify a big push to change.
We already have this. All current x86's have a decode unit to convert the x86 instructions to micro-ops in the native RISC instruction set.
Because X-rays are .01 - 10 nm light and EUV is 13.5nm light... so nothing to do with the word, as much as engineers like to label things correctly.
You are incorrect about the reason for lack of 3D stacking. Its not that we cant stack them. There has been a lot of work on it. In fact, the reason flash chips are increasing in capacity is because they are stacked usually 8 layers high. The problem quite simply is heat dissipation. A modern CPU has a TDP of 130W, most of which is removed from the top of the chip, through the casing, to the heatsink. Put a second core on top of it, and the bottom layer develops hotspots that cannot be handled. There are currently some approaches based on microfluidic channels interspersed between the stacked dies, but that has its own drawbacks.
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Um, actually Intel has done a lot of work on the architecture and microarchitecture of its processors. The CPUs Intel makes today are almost RISC like, with a tiny translation engine, which thanks to the shrinking size of transistors takes a trivial amount of die space. The cost of adding a translation unit is tiny, compared to the penalty of not being compatible with a vast majority of the software out there.
Itanium was their clean room redesign, and look what happened to it. Outside HPCs and very niche applications, no one was willing to rewrite all their apps, and more importantly, wait for the compiler to mature on an architecture that was heavily dependent on the compiler to extract instruction level parallelism.
All said, the current instruction set innovation is happening with the SSE, and VT instructions, where some really cool stuff is possible. There is something to be said for the choice of CISC architecture by Intel. In RISC ones, once you run out of opcodes, you are in pretty deep trouble. In CISC, you can keep adding them,making it possible to have binaries that can run unmodified on older generation chips, but able to take advantage of newer generation features when running on newer chips.
Legally obligatory sig : My opinions are my own... etc etc
Actually, 3D has picked up quite a bit in the last few years. However, the primary interest is connect different chips together in the same package with short, fast, interconnect. It's a lot better than conventional System In Package and much much better than circuit board connections. Unfortunately, the connections are a bit too coarse to spread a single design like an Intel processor across the layers.
For that you need more sophisticated methods like growing a new wafer on top of one that has already been built up. These methods are not yet ready for production.
I deal with EUV lithography for a living. Not at Intel, but at ASML, the world's largest supplier of lithography machines and the only one that has actually manufactured working EUV lithography tools.
Something thats been in development for even 5 years and doesn't show any concrete signs of success should at least have alternatives developed for it. After 5 years if you still can't say for certain if its ever going to work, you definitely need to start looking in different directions.
You are misinformed. On our Alpha development machines, working 22 nm devices were already manufactured last year. (source) We are shipping the first commercial EUV lithography machines in the coming year (source, source) A problem for the chip manufacturers is that the capacity on the alpha machines is rather low and needs to be shared among competitors.
There is a temporary alternative; it is called double patterning (and triple patterning, etcetera). The first problem is that you need twice (thrice) as many process steps for the small features, and also proportionally more lithography machines that are not exactly cheap. The second problem is that double patterning imposes tough restrictions on the chip design; basically you can only make chips that consist mostly of repeating simple patterns. That is doable for memory chips, but much less so for CPUs. Moreover, if you want to continue Moore's law that way, the manufacturing cost will increase exponentially, so this is not a long-term viable alternative.
You can bet that the semiconductor manufacturers have looked for alternatives. But those don't exist, at least not viable ones.
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IMEC is not the only ASML customer who has played with one of the two EUV Alpha tools, but it's the only one I could find with a quick Google search that has published the results. IMEC is a research institute. Other customers (actual chip manufacturers) have little to gain by disclosing to the competition exactly how much progress they have made.
Licensing is not the business model. The article suggests that Intel develops these machines ("fancy camera's") themselves, but in reality, they simply buy the machines from one of the three manufacturers (ASML, Nikon, and Canon). We spend an R&D budget of 500 M€ per year to develop these machines; Intel's R&D costs are likely mostly in the design of their chips and optimizing process parameters to squeeze as much as possible out of their fabs.
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I forgot to add a disclaimer: the opinions expressed are mine and not necessarily my employer's, etcetera.
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