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Chips That Flow With Probabilities, Not Bits

Posted by samzenpus on from the new-angle dept.

holy_calamity writes "Boston company Lyric Semiconductor has taken the wraps off a microchip designed for statistical calculations that eschews digital logic. It's still made from silicon transistors. But they are arranged gates that compute with analogue signals representing probabilities, not binary bits. That makes it easier to implement calculations of probabilities, says the company, which has a chip for correcting errors in flash memory claimed to be 30 times smaller than a digital logic-based equivalent."

5 of 153 comments (clear)

  1. Re:Analog Computers by Anonymous Coward · · Score: 5, Informative

    No, it does. We aren't trying to reduce error in logic operations. We're passing analog values between one and zero into logic circuits. Literally, at the lowest level, the "bits" pumping through the chip are probabilities. It's not analog in the sense that we use op amps, we still use gates, but the inputs and ouptuts of the gates are probabilities, not hard bits.

  2. The actual thesis by Mathiasdm · · Score: 4, Informative

    By Ben Vigoda, Co-Founder and CEO: http://phm.cba.mit.edu/theses/03.07.vigoda.pdf

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    1. Re:The actual thesis by Asic+Eng · · Score: 3, Informative
      Being a chip designer I quite frequently encounter articles which claim that there is going to be a "new way to design chips" coming soon. I'm admittedly a bit jaded hearing about another one.

      Often these approaches overstate the problems of current methodologies quite significantly. This thesis too, seems to hit the old favorites. Here is an example: In clocked digital systems, speed and throughput is typically limited by worst case delays associated with the slowest module in the system.

      This would be true if clocked digital systems would be restricted to a single clock. Some are, but the embedded devices I work on usually have half a dozen clocks or more. Some modules run with fairly high speeds, others at relatively low speeds - synchronizing them is not only a standard task, it's actually reasonably easy compared with other problems we face.

      Very closely related another of their claims: The larger the area over which the same clock is shared, the more costly and difficult it is to distribute the clock signal.

      Again - true in principle, but exaggerating the problem. It's not so difficult to distribute a clock over a large area if you allow skew between different areas. That might appear to defeat the purpose, but you really only need to interface reliably between those areas. Skew can even be helpful in some cases: if you send signal X from block A to be clocked-in by block B - then it helps if the clock arrives later at block B than at block A. Of course it's a disadvantage for a signal Y driven from B to A - but that signal might be faster (less logic to go through in block B). Modern design tools can automatically use clock skew to achieve better timing.

      One more: Building in redundancy to avoid catastrophic failure is not a cost-effective option when manufacturing circuits on a silicon wafer

      Well, we happen to do that regularly, it's cost-effective if you know what you are doing. There are parts of the chip which are much more likely to fail than others - RAMs are more prone to defects than ordinary digital logic. So as part of device testing defective areas of a RAM block can be mapped to a handful of spare cells. doubling every transistor as suggested in the thesis, is not necessary, obviously.

      Any of these "fundamentally new" approaches have to compete with the evolutionary solutions which people find for the same problems. That's hard because some of these are at least as clever as the "fundamental" ones, and they are much easier to adapt in existing design flows. I'm not ruling out that at some point we'll switch to a completely different design methodology, just as I'm not excluding the possibility that lighter-than-air travel will at some point find a place in commercial aviation again. I'm just not holding my breath.

  3. Re:1 AND 1 = 1 : 0.8 AND 0.6 = 0.7 by Anonymous Coward · · Score: 3, Informative

    It's called fuzzy logic [http://en.wikipedia.org/wiki/Fuzzy_logic].

    One way to define it is NAND(x,y) = 1-MIN(x,y)
    and the rest follows using usual logic rules.

    I have no idea if that's what they do though.

  4. Re:Probability in computers: it's called a float by Frequency+Domain · · Score: 4, Informative

    [...] Nowadays Bayesian calculations usually involve thousands of iterations[...]. The simulation then converges to the right answer.

    The convergence you refer to is asymptotic. In practice it takes about 10000 iterations to get around a 1% bound on a single probability point estimate, and a factor of a hundred for each order of magnitude improvement. On top of that, if you're dealing with multiple distributions the overall expectation is not just a simple function of the component expectations unless the whole system is linear, you need to use convolution to combine results. And on top of that, lots of interesting problems are based on order statistics, not means/expectations. Having hardware that correctly manipulates distributional behavior in a few CPU cycles would blow the doors off of MCMC.