Samsung Develops Power-Sipping DDR4 Memory

Alex writes with this excerpt from TechSpot: "Samsung Electronics has announced that it completed development of the industry's first DDR4 DRAM module last month, using 30nm class process technology, and provided 1.2V 2GB DDR4 unbuffered dual in-line memory modules (UDIMM) to a controller maker for testing. The new DDR4 DRAM module can achieve data transfer rates of 2.133Gbps at 1.2V, compared to 1.35V and 1.5V DDR3 DRAM at an equivalent 30nm-class process technology, with speeds of up to 1.6Gbps. In a notebook, the DDR4 module reduces power consumption by 40 percent compared to a 1.5V DDR3 module. The module makes use of Pseudo Open Drain (POD) technology, which allows DDR4 DRAM to consume just half the electric current of DDR3 when reading and writing data."

Comments

Re:How much power comparatively?

[NoSig]

Sleep mode leaves the ram powered but powers down most other things, is what I think he is saying. So ram may be the most significant power consumer for sleep mode.

POD explained

[overshoot]

In a classical open-drain connection, the active device pulls down and the bus termination pulls up. For a pure transmission line, this works just fine -- the current wave from the turn-off of the driver is effectively identical to the current wave from the turn on. In practice, open-drain uses more static current than a push-pull driver against a center termination and since the line isn't a pure transmission line (lumped capacitances, stubs) the rising edge is slower than the falling edge.

POD addresses this by actively pulling up at the beginning of a rising edge, then releasing the pullup to avoid a bus contention later. This reduces the termination current (at some cost in impedance mismatch, but it's already a sloppy line) and improved switching symmetry.

Nope

[overshoot]

One thing not mentioned in the article or summary is whether or not this technology reduces standby power consumption in DRAM.

POD by itself doesn't reduce power consumption in standby, since both POD and SSTL turn off the bus drivers then. The older POD technologies from the GDDR families use Thevenin termination, though, so the terminators draw a lot of unnecessary current when they're enabled (as distinct from the result with a dedicated termination supply.)

If you really want to know how this all works, JEDEC has the DDR4 standard available for free download. Follow the "free standards" link.