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Multi-Core Voltage Regulators To Increase Processor Efficiency
cylonlover writes "For decades, chipmakers strove to develop the fastest and most powerful chips possible and damn the amount of electricity needed to power them, but these days raw grunt isn't the only consideration. As more and more devices go mobile and these devices become more and more powerful, chipmakers must also take the energy efficiency into account. Harvard graduate student Wonyoung Kim has developed and demonstrated an on-chip, multi-core voltage regulator (MCVR) that he says could allow the creation of 'smarter' smartphones, slimmer laptops and more energy efficient data centers by more closely matching the power supply to the demand of the chip."
That's lame, even within their already lame marketing speech.
The three laws of thermodynamics:(1) You can't win. (2) You can't break even. (3) You can't even quit.
Does anyone know of a good software solution until this kind of thing gets baked into the hardware?
Right now I use RM Clock
(which hasn't been updated since 2008)
It drops voltages & multipliers lower than the standard intel/windows/BIOS options.
[Fuck Beta]
o0t!
... just a warning.
Including the same charts and graphs.
http://www.anandtech.com/show/1770
How this guy is going to get a patent on this stuff based upon his work in 2008 when Intel showed it onstage at IDF in 2005 is beyond me.
http://lkml.org/lkml/2005/8/20/95
http://www.powervation.com/
This company has a power control chip which has firmware which you can tailor to the hardware it is attached too. And its available to buy right now.
So this is a way for an ALU (say) to send a message to to the MCVR saying "we need ten trillion electrons" when it is asked to a floating point multiplication, then the electrons get parcelled out and the ALU shuts down when the job is done. Sounds reasonable but there is still going to be a voltage regulator off the chip. This is more like an intelligent distribution system.
http://michaelsmith.id.au
Sounds similar to SmartReflex (tm) which is shipping on millions of phones.
http://focus.ti.com/general/docs/wtbu/wtbugencontent.tsp?templateId=6123&navigationId=12032&contentId=4609&DCMP=WTBU&HQS=ProductBulletin+PR+smartreflex
Where it differs is that there is an on-chip regulator to do the dynamic scaling.
The TI solution has a couple of regulators on-chip, with a couple of output voltages, as well as a more variable external solution.
The above device has variable regulators on-chip. (for annoying technical reasons, these are linear regulators, not switching,
so if they regulate to 50% output - half the (reduced amount of power needed) is wasted as heat.
CPU manufacturers have been caring about power efficiency for a vasy long time.
In fact, the first version of the ARM processor (in the 80's) was designed around its power usage so that they could use a cheap plastic carrier, rather than a very expensive ceramic one like all the competeing chips.
SJW n. One who posts facts.
Nope it does not! ;-)
At least not running a fully up to date Firefox on a real OS
Translation:
After years of marketing magahurts we have now moved on... to marketing the number of cores. Of course in a phone most of these cores end up doing nothing most of the time, most of the real work is done on the baseband, so we need a circuit to shut down cores that we sold but are not being used.
Anyways, everyone knows 64 Cores ought be be enough for everybody
I confess I am totally underwhelmed. Every chip I have designed since the 1990s (mostly wireless chips with embedded MCUs and DSPs, for portable applications) has had multiple voltage domains with multiple, independently controlled, on-board linear regulators -- sometimes as many as six or eight of them. Each MCU (and/or DSP) core always has its own regulator; it's the only way to meet the power budget of a mobile/portable product. Sometimes the voltage is dynamically controlled in response to processing requirements, and sometimes (if the processing requirements are relatively constant) the regulated voltage is designed to vary with temperature, so that at all times only the minimum voltage needed is supplied. (And yes, sometimes switching regulators are used, if the electrical noise can be tolerated in the application.)
ISSCC isn't known for accepting junk papers, so I'm hoping that what was actually presented (I didn't attend this year) was a novel on-chip voltage-regulation technique, and that the journalist has done a disservice to Kim by emphasizing the application, rather than the real novelty of his work.
The real problem with these designs is the interfaces between cores operating at different voltages. It's a PITA to do all the level-shifting to ensure that a core operating at 0.5 V can communicate with one operating at 1.2 V, ensure that one shut down doesn't affect one still operating, etc. There are lots of corner cases to consider (including transient effects while voltages and computing loads are dynamically changing), and a new technique to handle that reliably would be an advance in the art.
The process monitoring CPU usage could be swapped out while a process that requires high CPU usage and hence a higher voltage is swapped in. Of course it won't get the higher voltage until the monitoring process is swapped back and by then its too late. Catch 22.
Does anyone remember intelligent processor cycling on mac portables? It guesses wrong and makes your games run clicky. Remember marathon on a 520c...
The purpose of existence is to make money.
Lotsa fuzzyness in this blurb. Let's see if we can help clarify:
(1) First, these are not "voltage regulators". in the usual sense of something that takes an unregulated voltage and provides a stable, regulated voltage. They're the opposite-- taking a relatively stable main battery bus and dropping it down to various lower and possibly varying voltages. The goal being to sacrifice some speed and noise margin in order to use less power.
(2) Next: putting voltage droppers on-chip inevitably leads to much lower efficiency-- the only way to efficiently drop voltage is to use a switching-mode regulator, which not only generates a lot of electrical noise, it requires a big hefty inductor and capacitor, neither of which can be made on-chip. This on-chip voltage-dropping scheme cannot be any more efficient that using a plain old resistor, where you end up wasting a lot of power to get to a lower voltage.
(3) Dropping the voltage is not the only way to save power. In a pure CMOS chip you can scale down the clock speed and the power usage goes down by the same factor. This is a whole lot simpler, reliable, and more power efficient than dropping the voltage.
Based on what gizmag presents I'm not terribly impressed. There are several reasons to put the VR offboard. First is space, second is heat. A VR consumes a lot of both (relative to a microprocessor). You can easily see >5" square of space and >10W of power dissipation next to the processor (and everyone cries about it because of its location).
Since I don't see any resonant components included in the design it appears to me that this is a linear regulator, which will put out a lot of heat. In addition as it stands both Intel and AMD have the ability to dynamically scale the voltage they are being powered from. They can request a higher or lower voltage as well as (of course) draw more or less current, instantly, through their VID pins. So this sure doesn't sound like a great discovery, especially when you consider that the basic concept, as presented in the summary, is widely used and quite well known. But summaries by their definition don't tell the whole story, so perhaps there's more to it. I'll pull up the paper if it's available when I get to work.
As chip-on-chip technology becomes more widespread I will be interested to see what happens. It seems like there may be a place for "on chip" (as far as the enduser is concerned) voltage regulation with some of these all-in-one converter MCMs.
Just my $0.55 (US inflation, 1774-2008, for $0.02)
This is slightly random, but how can I get my dual Pentium D to run at lower frequencies on Linux?
Perhaps it's yet another case of Academia "discovering" what someone in industry figured out a long time ago...
Now if it's a easy to fabricate buck converter, it might be interesting... we have to have those off-die. But I think fabricating those capacitors and inductors isn't easy.
-- Erich
Slashdot reader since 1997
This motivated me to look up some of Wonyoung Kim's papers. This one is a good overview of his research. Very nice work -- but almost unrecognizable from the Gizmag article.
I am Wonyoung Kim, the PhD student who designed the chip mentioned in the article. I heard my work was mentioned in slashdot and wanted to clarify several points.
- Per-core voltage control is not an old thing. Intel and AMD both do per-core frequency control, but not voltage control. Multiple cores share a single voltage in their processors. There is an opportunity for additional power savings if the voltage is controlled at a per-core basis to track per-core frequency changes.
- My design is not a linear regulator. It is a "3-level" DC-DC converter that is a hybrid between the buck and switched-capacitor converters. It uses a flying capacitor to enable a much smaller inductor than the buck, which is important for on-die integration.
- This chip is not the first to present the "3-level" design, but the first 3-level converter to integrate everything (including inductors and capacitors) on a single die.
- Fully integrated DC-DC converters can enable nanosecond-scale, per-core voltage control while not adding board-level components.
Feel free to send me any questions if you are curious to hear more details.
You can find my email by googling "wonyoung kim harvard".
I am Wonyoung Kim, the PhD student who designed the chip mentioned in the article. I heard my work was mentioned in slashdot and wanted to clarify several points. - Per-core voltage control is not an old thing. Intel and AMD both do per-core frequency control, but not voltage control. Multiple cores share a single voltage in their processors. There is an opportunity for additional power savings if the voltage is controlled at a per-core basis to track per-core frequency changes. - My design is not a linear regulator. It is a "3-level" DC-DC converter that is a hybrid between the buck and switched-capacitor converters. It uses a flying capacitor to enable a much smaller inductor than the buck, which is important for on-die integration. - This chip is not the first to present the "3-level" design, but the first 3-level converter to integrate everything (including inductors and capacitors) on a single die. - Fully integrated DC-DC converters can enable nanosecond-scale, per-core voltage control while not adding board-level components. Feel free to email me any questions if you are curious to hear more details.