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Intel Medfield SoC Specs Leak

MrSeb writes "Specifications and benchmarks of Intel's 32nm Medfield platform — Chipzilla's latest iteration of Atom and first real system-on-a-chip oriented for smartphones and tablets — have leaked. The tablet reference platform is reported to be a 1.6GHz x86 CPU coupled with 1GB of DDR2 RAM, Wi-Fi, Bluetooth, and FM radios, and an as-yet-unknown GPU. The smartphone version will probably be clocked a bit slower, but otherwise the same. Benchmark-wise, Medfield seems to beat the ARM competition from Samsung, Qualcomm, and Nvidia — and, perhaps most importantly, it's also in line with ARM power consumption, with an idle TDP of around 2 watts and load around 3W."

164 comments

  1. One benchmark by teh31337one · · Score: 2, Insightful

    It beats the current crop of dual core ARM processors (Exynos, snapdragon s3 and Tegra 2) in one benchmark that "leaked".

    Nothing fishy about that at all.

    1. Re:One benchmark by icebike · · Score: 4, Informative

      It beats the current crop of dual core ARM processors (Exynos, snapdragon s3 and Tegra 2) in one benchmark that "leaked".

      Nothing fishy about that at all.

      Quote Vrzone:

      Intel Medfield 1.6GHz currently scores around 10,500 in Caffeinemark 3. For comparison, NVIDIA Tegra 2 scores around 7500, while Qualcomm Snapdragon MSM8260 scores 8000. Samsung Exynos is the current king of the crop, scoring 8500. True - we're waiting for the first Tegra 3 results to come through.

      But the same paragraph says

      Benchmark data is useless in the absence of real-world, hands-on testing,

      If the performance figures are realistic this is one fast processor, and it appears to be a single core chip, (or at least I saw nothing to the contrary). That's impressive.

      Single cores can get busy handling games or complex screen movements, leading to a laggy UI. If they put a good strong GPU on this thing you might never see any lag.

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    2. Re:One benchmark by Nom+du+Keyboard · · Score: 1

      It beats the current crop of dual core ARM processors (Exynos, snapdragon s3 and Tegra 2) in one benchmark that "leaked".

      Nothing fishy about that at all.

      So it beats (maybe) the ARMs of the moment. But what about the ARMs when Medfield actually ships? And the quad-core ARMs now?

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    3. Re:One benchmark by teh31337one · · Score: 1, Redundant

      Sure, it's great, and compares well to this gen of processors (which are all at the 45/40nm fab (the exynos 4210 is 45nm, not 32nm as vr-zone incorrectly states)).
      But what about the next gen chips that will have 32/28nm fab?

      And how will it compare to the Quad-Core A9 processors (Tegra 3), higher clocked dual core A9 processors (Exynos 4212) or A15/A15 based designs? (Exynos 5250 and Krait/Snapdragon S4)

    4. Re:One benchmark by teh31337one · · Score: 0

      Exactly. And the current crop mostly have 45/40nm fab. How will it compare to the 32/28nm fab, quad core and A15 based ARM processors? Will Intel still be trying to get the power consumption down to acceptable levels then?

    5. Re:One benchmark by TheCouchPotatoFamine · · Score: 1

      What does the number of cores have to do with a "good, strong" GPU, or a lag of the UI? Lag is usually interrupt-based (think network or disk access), or the result of software, when operations are poorly ordered and/or uncached lookups perform often.. therefore your benchmark has a rabbit with a pancake on it's head -

      --
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    6. Re:One benchmark by icebike · · Score: 2

      At the stated bench mark scores Medfield IS THE NEXT GEN Chip.
      And its single core. When they dual well it, the others will still be trying hard to catch up.

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    7. Re:One benchmark by teh31337one · · Score: 1

      Great. How about comparing it to a NEXT GEN chip then? Not to mention power consumption - which is its Achilles heel - still can't compare to THE LAST GEN ARM CHIP.

    8. Re:One benchmark by icebike · · Score: 1

      If you have a good GPU, you can off load a lot of processing that might be otherwise have to do with the CPU. Sift enough work, and you can do with a single core what others might do with a dual. Thats all I was trying to point out.

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    9. Re:One benchmark by icebike · · Score: 1

      Actually go read the story. It specifically states that the power consumption is pretty close to the ARM chips.

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    10. Re:One benchmark by Dr+Max · · Score: 2

      I have no doubt in my mind that intel can beat chips that have been on the market for close to 12 months but the next crop is what they are competing against. For example texas instruments omap 5430 well be coming out a bit after this one sporting 2 X 2 ghz a15 chips, usb 3, sata 2, support for 4gb or ram per core, capable of running 4 screens at 1080p and it's printed on 28nm, that has to give old intel a run for their money. That said 2013 when intel move it down to 22nm trigate architecture and make it multi core its going to be interesting.

      --
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    11. Re:One benchmark by teh31337one · · Score: 4, Informative

      Yeah... no.

      vr-zone

      As it stands right now, the prototype version is consuming 2.6W in idle with the target being 2W, while the worst case scenarios are video playback: watching the video at 720p in Adobe Flash format will consume 3.6W, while the target for shipping parts should be 1W less (2.6W)

      extremeTech

      The final chips, which ship early next year, aim to cut this down to 2W and 2.6W respectively. This is in-line with the latest ARM chips, though again, we’ll need to get our hands on some production silicon to see how Medfield really performs.

    12. Re:One benchmark by Anonymous Coward · · Score: 5, Insightful

      I did read the story - but did you? Its idle TDP stands at 2.6W. A 1700mAH battery (typical in a cell phone) @ 3.6V = 6.12 Volt-Amps (i.e. Watts). So, you'll get around 2.5 hrs of uptime under idle conditions, assuming the battery is new. Good luck trying to charge that monster ever 2 hrs!
      Who cares about performance when your phone will be dead before making a single call? Not much better in tablets either!
      So, what is this chip competing against? Other laptop chips from Intel?

    13. Re:One benchmark by Anonymous Coward · · Score: 5, Insightful

      Yeah... no.

      vr-zone

      As it stands right now, the prototype version is consuming 2.6W in idle with the target being 2W, while the worst case scenarios are video playback: watching the video at 720p in Adobe Flash format will consume 3.6W, while the target for shipping parts should be 1W less (2.6W)

      extremeTech

      The final chips, which ship early next year, aim to cut this down to 2W and 2.6W respectively. This is in-line with the latest ARM chips, though again, we’ll need to get our hands on some production silicon to see how Medfield really performs.

      And which ARM SoC's idle at 2W? That's at least an order of magnitude greater than any ARM SoC - those typically idle at a few tens or hundreds of milliAmps. ARM's big.LITTLE architectures will bring that down even further.
      So, Medfield may be competitive on speed and TDP at full load, but if you are a mobile device maker, would you care? You would probably be more interested in eking out more uptime from your tiny battery.

    14. Re:One benchmark by LordLimecat · · Score: 4, Interesting

      According to what I could dig up (memory, and corroboration here), snapdragons use about 500mw at idle. Thats one quarter to one sixth the power consumption of intel's offering.

      Doing some research, it looks like Tegra3s use about .5w per core as well. Again, Intel is pretty far back if theyre throwing out a single core and hitting 2-3 watts.

    15. Re:One benchmark by Tr3vin · · Score: 3, Informative

      UI lag is almost exclusively limited to fill-rate on mobile devices. This is a problem on Android, since it is hard for them to optimize it for all of the various chipsets. If the GPU cannot quickly fill pixels, more of the preparation of a frame has to be offloaded to the CPU. For modern GUIs, each pixel can be touched several times, so without a good fill rate, more heavy lifting is required from the CPU. Multiple cores can help, since more processing power can be dedicated to quickly updating the UI.

    16. Re:One benchmark by gl4ss · · Score: 1

      it would be usable for tablets and media consumption devices, and devices which can hibernate quickly.

      of course there's this one nagging thing about using them for phones, which is.. well, fuck, they'd still need an arm chip or two there for the radios.

      --
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    17. Re:One benchmark by SuricouRaven · · Score: 1

      That's just powering the processor. You've got all the support chips, radio and such to. The single biggest power draw in most phones and tablets is the screen, when it's on - a good deal of power management goes into just trying to keep it turned off as much as possible.

    18. Re:One benchmark by Anonymous Coward · · Score: 1

      ...

      Doing some research, it looks like Tegra3s use about .5w per core as well. Again, Intel is pretty far back if theyre throwing out a single core and hitting 2-3 watts.

      not to forget, that tegra3 should use their special power-efficient 500MHz core for idle tasks...

    19. Re:One benchmark by Anne+Thwacks · · Score: 1

      I think there is a confusion between m and u here, or you are not talking about idle.

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    20. Re:One benchmark by AmiMoJo · · Score: 1

      I was about to say the same thing. A typical high end smartphone has a 1700mAh battery. That means 1.7A for one hour before the battery is depleted. A phone that idles at 2W will last less than an hour on a full charge, and that is assuming that the screen is off. I don't have tablet battery specs to hand but they won't be that much better.

      Android has a handy feature where you can check power consumption built in, and there are apps on the Market that can give you the real-time current consumption. At idle 0.01A for the CPU and radio is too high.

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    21. Re:One benchmark by hvdh · · Score: 1

      1700mAh at 3.6V (Lithium) is 6.1Wh, giving 3 hours at 2W power consumption. Still too short...

    22. Re:One benchmark by Anonymous Coward · · Score: 0

      We need to define ui lag. When I press a button and nothing happens for a second or two it sure isn't a fill rate problem.

    23. Re:One benchmark by Anonymous Coward · · Score: 0

      Nope. That's always been Intel's problem when it comes to their embedded SOCs. They always have very high power consumption compared to the competition. Performance has never been their issue. Basically this is another, who-gives-a-crap story for Intel CPUs.

      ARM CPUs are slower because they are dramatically more power efficient. That's the trade; best performance given best power efficiency for a given unit of work - or none. For whatever reason, Intel insists on wearing their stupid hat when it comes to this target audience.

    24. Re:One benchmark by LordLimecat · · Score: 3, Informative

      My mistake-- those numbers are at full load, not idle. That certainly doesnt help intel at all.

    25. Re:One benchmark by godefroi · · Score: 1

      Single cores can get busy handling games or complex screen movements, leading to a laggy UI.

      I know, right? The entire computer industry was plagued with these "laggy UI"s until multi-core processors were invented and saved us. If only someone had thought out a way to run multiple paths, or maybe call them "threads", of execution on a single CPU.

      Oh well, too late for that.

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    26. Re:One benchmark by Anonymous Coward · · Score: 1

      Actually go read the story. It specifically states that the power consumption is pretty close to the ARM chips.

      Then the story was written by idiots who don't know what they're talking about. The dual-core ARM chips the benchmarks compared this chip to typically consume less than 1W under load, and just a handful of milliwatts at idle. Scale that out to the quad-core chips you'll need to beat its performance, and you've got a chip consuming about half as much at load and probably just a handful of percent as much at idle. The freescale iMX 6 consumes 350mW decoding full-HD video (the same task that this processor needed 3.6W for). This is not, by any reasonable definition, "pretty close".

    27. Re:One benchmark by TheRaven64 · · Score: 1

      No, it talks complete bullshit. The idle power consumption is 2W! The full-load power consumption of a typical ARM SoC (including CPU and GPU) is usually under 2W. Idle power consumption is generally well under 100mW, typically closer to 20mW. It's 'pretty close' if you mean 'within two orders of magnitude'. Or as we would normally say 'not close at all.'

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    28. Re:One benchmark by TheRaven64 · · Score: 1

      UI lag is when you press the button and the button press animation doesn't happen immediately, or you drag something and the screen is not updated immediately. If you press a button and nothing other than the UI being updated happens then it's just slow code, not a laggy UI.

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    29. Re:One benchmark by Anonymous Coward · · Score: 0

      Not sure what these numbers represent, but it seems clear to me they do not represent the SoC power during idle. Look at Medfield's predecessor (Moorestown):

      Moorestown Battery Life (Figures by Intel) Total Phone Power Consumption
      Idle 21 - 23 mW
      Audio Playback 120 mW
      1080p Video Playback 1.1W+
      Web Browsing (WiFi) 1.1W
      2G Phone Call 550 mW
      3G Phone Call 1.2W

      Source: http://www.anandtech.com/show/3696/intel-unveils-moorestown-and-the-atom-z600-series-the-fastest-smartphone-processor/12

      We can assume that Medfield will have = idle power to it's predecessor.

    30. Re:One benchmark by spatular · · Score: 1

      Well, single-core, 65nm, 600MHz OMAP3 in n900 consumes about 90mA@3.7V (~300mW) under full load, and about several mA when idle. 2W at idle and concept of smartphone are not really compatible. This CPU will discharge a typical 4W*h battery in 2 hours. And here It doesn't really matter if it is 10% or 100% faster then an ARM SoC.

  2. Still need to wait for more figures... by inflex · · Score: 1

    The Atom's have always had a reasonable core power consumption... but the external chipsets that ruin the system power consumption figure. Will be curious to see what the total system consumption is going to be with these new one, maybe time to look towards a nice replacement for my Asus eeebox B202's for the desktop.

    1. Re:Still need to wait for more figures... by the+linux+geek · · Score: 1

      It's a SoC. No external chipset necessary.

    2. Re:Still need to wait for more figures... by timeOday · · Score: 1
      The point of Medfield is to integrate the external chipsets. They aren't there any more, so I don't see where system power consumption would be at any disadvantage to an ARM chip.

      It's hard to imagine how Intel could not win this, now or soon. They have the best chip designers and process.

    3. Re:Still need to wait for more figures... by inflex · · Score: 2

      For sure, yes, it's a SoC, but I'm still going to wait for a complete "on the shelf" system to make an appearance before holding my hopes too high. Leaked releases are about as useful as "New solar cell technology yields 50% more efficiency" announcements.

      What is interesting is that they only mention the elevated power consumption in relation to video playback (720p) which is something that'd likely be handed off to a dedicated section of silicon, not something done in the general purpose CPU core. Hopefully we can get some more comprehensive data soon so we can all stop speculating.

    4. Re:Still need to wait for more figures... by darronb · · Score: 2

      Well, the limiting factor is quite certainly backwards compatibility.

      The architecture itself very possibly cannot compete with ARM on low power... no matter what the "best chip designers and process" can bring to the table.

      I think it's getting to be time to finally retire x86. It'll be hell to bring a new architecture to market... but what's the alternative? Microsoft is dying. Apple is starting to make their own chips.

      They probably do have the best people and starting fresh they could very likely do amazing things.

    5. Re:Still need to wait for more figures... by mollymoo · · Score: 1, Insightful

      x86 is a a huge, complex instruction set. All else being equal. implementing it costs more silicon and more power than ARM architectures. Intel's great engineers and unmatched process can make up for this somewhat, but it would be a good effort for them just to achieve parity with ARM. To do so they're likely going to need to stay one process step ahead of the competition, which has cost implications.

      --
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    6. Re:Still need to wait for more figures... by Belial6 · · Score: 1

      The solution is actually pretty straight forward. Multi-core is the present. To make a complete clean sweep, the solution is for Intel to make a processor that has say, 4 x86 cores, and 2 xWayBetterThan86 cores. They then design the system to allow code that is written for the xWBT86 cores to run in parallel with the x86 cores. Get MS to port Windows to use the xWBT86 cores for the OS, and advocate to the developers. Basically turn the old x86 into a legacy compatibility co-processor. They would want to contribute the code necessary to make this happen on Linux while they were at it.

      Since in theory, the xWBT86 cores would be Way Better Than the x86 cores, software developers would want to write code that runs on them, and the x86 legacy cores would become less and less necessary. As demand dictates, Intel could then start reducing the number of x86 cores, and increasing the number of xWBT86 cores. When demand for x86 gets low enough, they could switch to emulation.

      If they really wanted to make it slick, they could design the chips so that the cores could be changed from x86 to xWBT86 by swapping out the microcode. The x86 command set is basically emulated now anyway.

    7. Re:Still need to wait for more figures... by timeOday · · Score: 1

      The first x86 processor, the 8086, only had 29,000 transistors total, whereas this new chip uses over 34,000 times that many (a billion) just for DRAM, so how much complexity can x86 really be adding? Too many other architectures have come and gone - 68K, PowerPC, SPARC, ARM on the desktop... whatever advantage they gained from more elegant architecture wasn't enough to overcome x86s' 30 years of refinement and Intel's lead in process and design. With Itanium, even Intel itself massively blundered over-estimating what they could get from a redesign.

    8. Re:Still need to wait for more figures... by Anonymous Coward · · Score: 1

      Didn't Transmeta design a xWBT86 architecture?

    9. Re:Still need to wait for more figures... by Anonymous Coward · · Score: 0

      So just like Itanium then? Where the x86 mode was so slow you could do it faster in software? Or the i860 before it, which could take up to somewhere around 2000 cycles to refresh it's multiple pipelines? (Not to mention both Itanium and i860 were VLIW, so you couldn't practically do any optimization to take advantage of the super-scalar pipeline.) Or the i960 before that, where they got sued halfway through and decided not to market the whole processor in exchange for a settlement which gave them the StrongARM? Or the iAPX 432 before that, which was so big it broke the chip in two because they decided to make an object oriented processor?

      It's not that Intel is having problems moving away from x86, it's that Intel can't make anything better to move towards. x86 was just a nice little fluke which got them enough design wins to make it their breadwinner. Whenever they do try to make a better ISA, they wind up jumping on the latest fad without having any idea of how to properly implement it or even if it is a good idea in the first place.

    10. Re:Still need to wait for more figures... by jones_supa · · Score: 1

      The Atom's have always had a reasonable core power consumption... but the external chipsets that ruin the system power consumption figure. Will be curious to see what the total system consumption is going to be with these new one, maybe time to look towards a nice replacement for my Asus eeebox B202's for the desktop.

      I thought that problem was only with the early Atoms paired the 945GSE, and then later Pine Trail included the power-proper NM10 chipset.

    11. Re:Still need to wait for more figures... by Anonymous Coward · · Score: 0

      I'm not quite sure where you got the "Microsoft is dying" part from. They are making record profits. They are doing the opposite of dying.

    12. Re:Still need to wait for more figures... by SuricouRaven · · Score: 1

      I think it's more a matter of not growing. They have a slight problem. Their main cash cows are desktop operating systems and office software, and when you have nearly 100% of the market, the only way to grow is to grow the market. That takes a long time. Microsoft is thriving, but they can't give the massive year-on-year growth of their earlier success any more. Their efforts to enter new markets have been less than successful... the xbox is a respectable console, but the Zune was a joke, and Windows Mobile is barely even seen.

    13. Re:Still need to wait for more figures... by makomk · · Score: 2

      The first x86 processor, the 8086, only had 29,000 transistors total, whereas this new chip uses over 34,000 times that many (a billion) just for DRAM, so how much complexity can x86 really be adding?

      The 8086 was a 16-bit processor that could only address 1 MB of RAM (split up into 64k segments) with no support for virtual memory, didn't have any floating point hardware let alone stuff like SSE, and took an awfully large numbers of clock cycles to execute each instruction by modern standards. If you want something capable of actually running modern applications, you're looking at a lot more complexity.

    14. Re:Still need to wait for more figures... by rev0lt · · Score: 1

      I won't argue that ARM architectures are probably simpler to implement (chipwise) than Intel's x86/ADM64. What is usally called x86 instruction set is actually a blend of multiple instruction sets of different generations of processors, but most instructions aren't implemented in silicon, and Intel clearly describes it in the architecture manuals. CISC instructions are decoded in "micro-ops" (internal RISC instructions) and then those instructions are fed to the execution pipelines. You have microcode updates for "upgrading" the translation mechanism and, if needed, correct bugs on existing instructions. The instruction by itself set isn't directly related to the complexity of the processor (usually data/address paths and register size ARE the limiting factors).

    15. Re:Still need to wait for more figures... by Guy+Harris · · Score: 1

      Didn't Transmeta design a xWBT86 architecture?

      No, Transmeta designed two VLIW architectures that were, I think, incompatible with each other, and implemented x86 emulators atop them (simulated x86 and translated frequently-run code from x86 to the native architecture). Developers didn't {write code for, compile code into code for} the internal architectures; the chips were just used as alternative implementations of x86.

  3. 2 watts idle? by viperidaenz · · Score: 5, Funny

    Awesome, with smartphones these days containing 6 watt-hour batteries you'll get 3 hours standby time! Thats nearly as much an an iPhone 4S

    1. Re:2 watts idle? by Ark42 · · Score: 1

      I think batteries are rated in mAh, not mWh. For example, my Netbook has a 6600mAh battery that outputs 11.1v. I think that's basically 73.26Wh, or 36 hours of idle time at 2W. I don't have any smartphone to compare, nor do I know the actual idle usage of the Atom CPU in my netbook, or the other components in it.

    2. Re:2 watts idle? by Anonymous Coward · · Score: 0

      my evo4g battery shows 5.55 watt hours on its label.

    3. Re:2 watts idle? by Anonymous Coward · · Score: 0

      I think batteries are rated in mAh, not mWh.

      Either/both; given a nominal voltage, they're practically equivalent.

      For example, my Netbook has a 6600mAh battery that outputs 11.1v. I think that's basically 73.26Wh, or 36 hours of idle time at 2W.

      So I guess you knew that after all...
      (And you do realize your 9-cell netbook battery is an order of magnitude bigger than a phone battery, yes?)

      I don't have any smartphone to compare, nor do I know the actual idle usage of the Atom CPU in my netbook, or the other components in it.

      So why even post? FYI, they're all 3.7V, and mostly 1.2-2.4Ah, or 4-8 Wh -- so GGP was right on, and the only thing you've added to the discussion is a vigorous display of your own ignorance.

    4. Re:2 watts idle? by Ark42 · · Score: 1

      I guess I figured smartphones might have a bigger battery than my RAZR's 3.7v 900mAh.

      1200-2400mAh for something that does all kinds of applications and web access seems pretty small if 900mAh is what they give phones to people who don't even care about texting.

    5. Re:2 watts idle? by Anonymous Coward · · Score: 0

      I think batteries are rated in mAh, not mWh. For example, my Netbook has a 6600mAh battery that outputs 11.1v. I think that's basically 73.26Wh, or 36 hours of idle time at 2W. I don't have any smartphone to compare, nor do I know the actual idle usage of the Atom CPU in my netbook, or the other components in it.

      A typical smartphone has a 2000mAh, 3.7v battery == 7.4Wh, or a little over 3.5 hours idle at 2W.

  4. 2W idle power consumption! by Anonymous Coward · · Score: 2, Interesting

    That just doesn't cut it. Based on that, I'd assume the mobile version of the chip to consume at least 1W at idle loads. That _still_ doesn't cut it.

    1. Re:2W idle power consumption! by Baloroth · · Score: 1

      It gets worse: the summary is actually misleading. They benchmarked it around 2.6 idle and 3.6 active ("around", right), and it "aims" to get down to 2W idle and 2.6 active by next year.

      --
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    2. Re:2W idle power consumption! by Baloroth · · Score: 2

      Oops, my first "around" should have been "at". As in, they benchmarked it exactly at 2.6W and 3.6W idle and active, respectively (and rounded it down - way down - in the summary)

      --
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    3. Re:2W idle power consumption! by mirix · · Score: 4, Insightful

      Bingo. My ageing Nokia, while lacking in horsepower, has excellent battery life... It has a 600MHz ARM, and a 3.2Wh battery. It manages to idle for a week at least, I'm sure it's hit 10 days before, but lets say 7, to be safe.

      3.2W / 7 / 24 = 20mW idle. Two fucking orders of magnitude better than their *target*. (not to mention this includes the entire phone, not just the core, in real life).

      I presume the more powerful android rigs still keep it within 100mW for the whole phone, idling. - That would give you roughly two days idle on a decent sized phone battery (5Wh). That's still more than an order of magnitude difference.

      --
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  5. Looks cool by symbolset · · Score: 1

    I think the tablet will be interesting.

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  6. Its not just a phone, its a handwarmer by Anonymous Coward · · Score: 1

    Its a feature!

    2W idle + 3W active?!!!

    Not in line with power consumption of any ARM board I've played with-- more like 4-6 times active consumption and an order of magnitude+ higher idle.

    But, if they can pull decent marketing of a portable hand warmer that doubles as a phone for a couple hours a day between charges, maybe they have a winner.

  7. beat ARM on what, 45nm? by Locutus · · Score: 3, Interesting

    come on, when talking about comparing embedded SoC's is it really fair to say a new die shrunk version of another architecture best another using a much larger die size?

    So here we have Intel putting their low cost product on their high cost process and claiming a victory? I don't buy it but since Intel is going to be selling these things at deep discounts, I might buy a product or two. I don't think in the long run they can continue this game but it's fun to see them attempting it.

    LoB

    --
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    1. Re:beat ARM on what, 45nm? by Anonymous Coward · · Score: 0

      Intel is ahead of the pack in manufacturing technology, so yes it is fair as far as the market is concerned.

    2. Re:beat ARM on what, 45nm? by Kjella · · Score: 2

      So here we have Intel putting their low cost product on their high cost process and claiming a victory?

      Developing the process is ungodly expensive, pushing out chips is not. Why wouldn't Intel use their state of the art process? It's not like it would be cheaper to produce on 40/45nm, far from it.

      I don't think in the long run they can continue this game but it's fun to see them attempting it.

      Well, it's the game Intel's been running since the 1980s and has kept AMD a distant second even when their chip designers have been smoking crack. Smaller process = more dies/wafer and so higher margins and more money to funnel back into R&D.

      Do I believe everything Intel says? Hell no. But their tick-tocks have been steady as clockwork, while for example graphics cards are now finally starting to move off 40nm with the HD7970. Intel's never had to cancel a process to my knowledge, like TSMC had to scrap their 32nm process. And recently GloFo was in the news because AMD had to scrap their 28nm process and start over at TSMC with gate-last. That burns vast amounts of cash and delays your products for a double kick in the balls. Meanwhile apparently Intel got a die shrink to 22nm and 3D transistors ready to go, since specs and prices for Ivy Bridge have been leaking all over the place. Can Intel do low-power design? Yes. No. Maybe. But if they can keep their process improvements coming on time and with decent yields, they'll be hell to compete with anyway.

      --
      Live today, because you never know what tomorrow brings
    3. Re:beat ARM on what, 45nm? by darkmeridian · · Score: 1

      High cost process? The more you shrink the die, the cheaper it gets to produce. Once the R&D and fabs have been done, you want to move everything to the smaller process if the yields are okay. Smaller dies mean that you get more chips per wafer. That means lower costs.

      --
      A NYC lawyer blogs. http://www.chuangblog.com/
    4. Re:beat ARM on what, 45nm? by Anonymous Coward · · Score: 0

      High cost process... Heh. Below 40nm is high cost to the ARM manufacturers. Intel process tech is in a different league entirely.

    5. Re:beat ARM on what, 45nm? by RightSaidFred99 · · Score: 1

      "Fair"? Huh? You compare products against each other based on performance and price. If one product is on a superior manufacturing process that is a differentiating advantage. Your post makes absolutely no sense.

      Besides, some ARM implementations will be on 32nm soon if it isn't already. Really Medfield is a stop-gap. The really interesting time will be when/if Intel puts the Atom chips on first-class manufacturing capacity. Tri-gate 22nm Atom chips would be very competitive.

    6. Re:beat ARM on what, 45nm? by Anonymous Coward · · Score: 1

      Huh? Intel's certainly got state of the art manufacturing facilities, but the list of ARM licensees also reads like a "who's who" of the IC manufacturing industry:

      http://www.arm.com/products/processors/licensees.php

      It's also hard to see Intel wanting to use all their capacity churning out smartphone CPUs that sell for a fraction (1/10?) of the the price of desktop chips. The volume of ARM-based chips that are sold annually is staggering - billions - they are in essentially EVERY consumer electronic device other than desktop/laptop computers.

    7. Re:beat ARM on what, 45nm? by rev0lt · · Score: 1

      Smaller dies means more defects per wafer. And electric problems at subatomic level. And defects that may manifest only when voltage is applied (leaking electrons, capacitance problems, etc). Also, smaller dies means that the specs for the raw materials are tightened, so it usually translates to "more expensive".

    8. Re:beat ARM on what, 45nm? by Locutus · · Score: 1

      It just seems that process advantages are short lived and everyone knows if you shrink the die you get better performance and power usage. But I get it that Intel bets its business on process and not processor design. I also get that many of the ARM vendors hire out their process and some companies are not too far behind Intel so if Intel gets a speed/power advantage over ARM it won't be long before ARM is back and will probably always beat Intel on price.

      competition is always good.

      LoB

      --
      "Anyone who stands out in the middle of a road looks like roadkill to me." --Linus
    9. Re:beat ARM on what, 45nm? by currently_awake · · Score: 1

      It doesn't matter how fast it is if the power consumption is over 1W it won't be used in phones. The only way Intel could beat ARM (on phones/tablets) is by inventing a better battery.

  8. better be able to add more (external) RAM by Anonymous Coward · · Score: 0

    > The tablet reference platform is reported to be a 1.6GHz x86 CPU coupled with 1GB of DDR2 RAM,

    For tablets / netbooks, you better be able to add more RAM. My current tablet came with 2GB, but supports up to 4, which is what I have it at now (cheap upgrade). RAM often makes more difference to system responsiveness than CPU speed. 1GB is fine for phones but just isn't much for tablets and netbooks.

    1. Re:better be able to add more (external) RAM by Kjella · · Score: 1

      1GB is fine for phones but just isn't much for tablets and netbooks.

      From "640kb is enough for everybody" (okay, maybe he didn't say it) to "1GB is fine for phones" in 30 years. I so badly want to go back with a time machine and show them one, and after they're amazed and all that and ask what kind of important things we use it for I'll just say "well, mostly we use it to play Angry Birds".

      --
      Live today, because you never know what tomorrow brings
  9. no AM? by decora · · Score: 2

    think of all those amplitudes not being modulated.

    this is a terrible, terrible loss for America.

    1. Re:no AM? by Anonymous Coward · · Score: 0

      He's on FM as well, you know.

    2. Re:no AM? by Anonymous Coward · · Score: 0

      I don't understand why it's not HD radio?

  10. whoosh by decora · · Score: 4, Insightful

    teh37737one's point, if i may, was that this 'leak' was actually a 'plant', a PR move by Intel to get people posting ridiculous speculative nonsense, like, exactly the stuff you posted in your comment.

    "if this is realistic, intel has an awesome CPU" etc etc etc.

    Does anyone care if its realistic? Intel sure doesn't, it just wants people to speculate that it might be realistic, and then talk about Intel, and how awesome Intel is.

    But of course, it might be a load of crap... when the actual numbers come out, who knows what they will say? And when real programs hit the thing, who knows what it will do?

    That's why Intel is 'leaking' it. On purpose. So they can have 'plausible deniability'. They can churn the rumor mill, get their product mentioned in the 24 hour ADHD cycle of tech news, get people posting on slashdot, etc, but Intel itself never has to sully it's good name by engaging in outright pushing of vapor-ware.

    If only the guys at Duke Nukem had been smart enough to 'leak' stuff 'anonymously' to the press, instead of giving out press releases...

    Of course, another way to look at it is this: It's yet another example of the corporate philosophical suite that is drowning our civilization in garbage and awful values. Never say anything directly, never take responsibility for your words or actions, never be straight with people, and hide everything you are doing in layers and layers of techno jargon, babble, and nonsense.

    1. Re:whoosh by Jeremi · · Score: 3, Insightful

      Does anyone care if its realistic? Intel sure doesn't

      Intel will care if the leaks create unrealistic expectations that their product can't meet. The result could be consumer rejection of an otherwise respectable product, because the public had been (mis)led to expect more than the product could actually deliver. (see: Itanium as replacement for x86)

      So the "secret Intel propaganda strategy" only works if Intel actually has a reasonable chance of living up to their own unofficial hype. And based on their recent track record, they probably do.

      --


      I don't care if it's 90,000 hectares. That lake was not my doing.
    2. Re:whoosh by Svartalf · · Score: 4, Informative

      Recent track record... Yeah, sure...

      http://www.pcper.com/reviews/Graphics-Cards/Larrabee-canceled-Intel-concedes-discrete-graphics-NVIDIA-AMDfor-now

      There's a few others like this one. This includes the GMA stuff where they claimed the Xy000 series of GMA's were capable of playing games, etc. They're better than their last passes at IGPs, but compared to AMD's lineup in that same space, they're below sub-par. Chipzilla rolls out stuff like this all the time. Been doing it for years now.

      Larrabee.
      Sandy Bridge (at it's beginnings...).
      GMA X-series.
      Pentium 4's NetBurst.
      iAPX 432.

      There's a past track record that implies your faith in this is a bit misplaced at this time.

      --
      I am not merely a "consumer" or a "taxpayer". I am a Citizen of the State of Texas
    3. Re:whoosh by Anonymous Coward · · Score: 0

      Does anyone care if its realistic? Intel sure doesn't

      Intel will care if the leaks create unrealistic expectations that their product can't meet.

      Bullshit. If this were true, why would they be hyping Medfield as a serious competitor to ARM (in real press releases, not just possibly-deliberate leaks) when they "hope" to get the idle power down to two fucking watts?! How much more unrealistic can you ask for?

      To Intel,, perception is everything, reality is nothing -- as proven by their continuous predominance in the desktop despite AMD's frequent performance-per-dollar and performance-per-watt lead, and occasional absolute performance lead. We can only hope this bean-counter's strategy fails at breaking into markets as spectacularly as it has succeeded in defending entrenched markets.

    4. Re:whoosh by 0123456 · · Score: 3, Informative

      To Intel,, perception is everything, reality is nothing -- as proven by their continuous predominance in the desktop despite AMD's frequent performance-per-dollar and performance-per-watt lead, and occasional absolute performance lead.

      Ah, yes. No-one ever buys Intel chips because they're the best option, poor old AMD keep building the best x86 chips on the planet but stoopid consumers keep buying Intel anyway.

      Back in the real world, at the time when AMD were the best choice you could hardly find anyone at all knowledgeable who was recommending Intel Pentium-4 space-heaters, and now that Intel is the best choice for desktop systems the only people recommending AMD CPUs are the dedicated fanboys. And in the low-power space, no-one uses Intel x86 CPUs because that would be absurd; even a 2W CPU can't compete against ARM.

    5. Re:whoosh by Xeranar · · Score: 1

      Intel kept AMD down by signing huge discounted contracts with OEM manufacturers. That's the reality of how Intel won. The consumer had basically a plethora of names and configurations when the PC came around as a major player but 90% of on the shelf boxes were Intel inside. AMD never was able to sign a huge contract and thus was kept out of the office and shelf space. It wasn't like Intel had vastly better chips until the i-series and even now under the $220 range they aren't really that better, specially considering the average PC is using an i3 chip. It's a game of Intel leveraging vast resources and thin margins to marginalize other players. ARM manufacturers are too large to undercut substantially though and will not take Intel lying down. This medfield processor feels more inclined to be in a semi-stationary position like a light notebook or tablet rather than a mobile phone. But who knows? Maybe Intel will get it's TDP down and do dual-core running at half that wattage...

    6. Re:whoosh by Anonymous Coward · · Score: 0

      Yes because I am sure Samsung, Apple, Nokia, and other OEMs are freaking out right now over this. "OMG look at that power consumption, stop buying the ARMS at once!!!!1"

      I have yet to run across someone who gives a shit which manufactures' CPU is powering their phone.

    7. Re:whoosh by GreatBunzinni · · Score: 1

      You appear to be confused. If you take the time to check the stores and compare AMD's offering to Intel's in terms of processing power and cost, you will learn that AMD's offerings are constantly the best ones in the market. More precisely, you will learn that:

      • AMD's processors, for the same price, pack more processing power per core than Intel's
      • AMD's processors, for the same processing power, are cheaper than Intel's
      • AMD's processors, for the same price, pack more cores than Intel's

      Then, once we factor additional costs such as motherboards, RAM and whatnot, you will realize that Intel's price tag is far higher than AMD, and this for a product which is inferior.

      Granted, Intel does produce the fastest chips out there. Yet, in this day and age where real-world performance (i.e., games, media work and the like) is dictated by the GPU and not the CPU, even today's mid to low-end processor can play the most demanding games. So, in practice no one actually has the need to purchase Intel's top of the line CPU, besides e-penis boasting. And to do that you have to shovel over 1k euros for the processor alone, in a day and age where 400 euros already purchase an entire desktop computer.

      So, exactly where are AMD's products not the best choice in the market? And who exactly is the fanboy here?

      --
      Slashdot, fix your code or at least hire someone who is competent at it to do it for you.
    8. Re:whoosh by Cid+Highwind · · Score: 1

      AMD's processors, for the same price, pack more power per core than Intel's

      Yeah, 10+ watts per core more than Sandy Bridge at full load!

      --
      0 1 - just my two bits
  11. apples and oranges? by viperidaenz · · Score: 3, Interesting

    It looks like CaffeineMark 3 is single threaded. At least the online version is anyway.
    How can you compare a 1.6ghz presumably single core against dual core cpus on a single thread benchmark?

    I just compared my laptop which is 2.2ghz dual core with my desktop, 3ghz single core. laptop gets 16,000, desktop gets 24,000. Laptop was at 50% cpu, desktop was at 100%.

  12. Why is the processor named "Medfield" by roarkarchitect · · Score: 1

    I was hoping someone would know ?

    1. Re:Why is the processor named "Medfield" by Anonymous Coward · · Score: 0

      It's just a code name. Don't worry about it too much.

    2. Re:Why is the processor named "Medfield" by QuantumRiff · · Score: 1

      http://en.wikipedia.org/wiki/List_of_Intel_codenames

      Most are named after bodies of water, and they used to all be rivers in the Pacific Northwest of the US, but they ran out, (and moved some development out of Portland, OR)

      --

      What are we going to do tonight Brain?
    3. Re:Why is the processor named "Medfield" by roarkarchitect · · Score: 1

      I live in "Medfield" and it's a unique town name. Members of the town have been trying to figure out how it got named.

  13. It's not Intel's high cost process by Sycraft-fu · · Score: 4, Informative

    These days 32nm is their main process. They use 45nm still but not for a ton of stuff. Almost all their chips have moved to it. Heck they have 22nm online now and chips will be coming out rather soon for it (full retail availability in April).

    Once of Intel's advantages is that they invest massive R&D in fabrication and thus are usually a node ahead of everyone else. They don't outsource fabbing the chips and they pour billions in to keeping on top of new fabrication tech.

    So while 32nm is new to many places (or in some cases 28nm, places like TSMC skipped the 32nm node and instead did the 28nm half node) Intel has been doing 32nm for almost 2 years now (first commercial chips were out in January 2010).

  14. Just let x86 die, please. by VortexCortex · · Score: 3, Interesting

    It's bloated. It had its time. I LOVED writing in assembly on my 80286, the rich instruction set made quick work of even the most complex of paddle ball games...

    However, that was when I was still a child. Now I'm grown, it's time to put away childish things. It's time to actually be platform independent and cross platform, like all of my C software is. It's time to get even better performance and power consumption with a leaner or newer instruction set while shrinking the die.

    Please, just let all those legacy instruction's microcode go. You can't write truly cross platform code in assembly. It's time to INNOVATE AGAIN. Perhaps create an instruction set that lets you get more out of your MFG process; Maybe one that's cross platform (like ARM is). Let software emulation provide legacy support. Let's get software vendors used to releasing source code, or compiling for multiple architectures and platforms. Let's look at THAT problem and solve it with perhaps a new type of linker that turns object code into the proper machine code for the system during installation (sort of like how Android does). DO ANYTHING other than the same old: Same Inefficient Design made more efficient via shrinking.

    Intel, it's time to let x86 go.

    1. Re:Just let x86 die, please. by Anonymous Coward · · Score: 0

      I mostly agree with you, but the trouble for intel with emulation (which is slow already) is that it's quite slow *before* you add in a dramatic scale-down in factor (from desktop/laptop to tablet/cell phone). Emulated x86 apps written for w32api are not going to get any kind of useful performance on an ARM emulating an x86, period.

    2. Re:Just let x86 die, please. by the_humeister · · Score: 1

      Hahahaha... oh wait, you're serious.Ok, so what high performance, low-cost, and power efficient processor should we all migrate to then? And will you pay to have all my software ported over to this new ISA?

    3. Re:Just let x86 die, please. by Anonymous Coward · · Score: 0

      About the only thing cisc about x86 is its front end. The rest is an out of order, speculative, 3-4 instructions at a time, risc instruction set.

      The CISC vs RISC is a moot point at this point. ARM is better on the power draw because of one thing. It has about 1/2 the transistor count (less heat less current leakage). It is also a slower processor because of it. Intel is going to beat ARM at its own game. It even has a new '3d' sort of transistor to do it with. TSMC does not have that tech.

      Also the more layers you add in the more latency you add. All the 'cool' performance critical apps on android use the NDK not the SDK.

      I used to think as you. That mips was going to whip the snot out of everyone. Didnt happen. Then it was powerpc, the it was... see a pattern?

    4. Re:Just let x86 die, please. by AcidPenguin9873 · · Score: 4, Interesting

      I scoured your post for one actual reason why you think x86 is an inferior ISA, but I couldn't find any. I'll give you a couple reasons why it is superior, or at least on par with, any given RISC ISA, on its own merits, not taking into account any backwards compatibility issues:

      • Variable length instruction encoding makes more efficient use of the instruction cache. It is basically code compression, and as such it gives a larger effective ICache size than a fixed length instruction encoding. Even if you have to add marker bits to determine instruction boundaries, it's still a win or at least a wash.
      • x86 has load-op instructions. Load-op is a very, very common programming idiom both for hand written assembly and for compiler generated code. ARM and other RISC ISAs require two instructions to accomplish the same thing.
      • AVX, the new encoding from Intel and AMD, gives you true RISC-like two source, one non-destructive dest instructions.
      • Dedicated stack pointer register allows for push/pop/call/return optimizations to unlink dependence chains from unrelated functions. With a GPR-based stack, RISC has false dependence problems for similar code sequences that they can't really optimize,
      • AMD64 got rid of cruft, added more GPRs, and added modern features like PC-relative addressing modes, removing that advantage from RISC too.
      • ARM's 64 bit extensions were just announced and won't be shipping until 2014. x86 has been 64 bit for 8 years.

      x86 should be able to compete quite well with any RISC ISA on its own merits today.

    5. Re:Just let x86 die, please. by Anonymous Coward · · Score: 2, Informative

      1. Having variable length instructions complicates instruction decoding, which cost die space and cycles (once for actual decoding and once for instructions spanning fetch boundaries). Also several processor architectures save 16-bit instructions (ARM, SH, MIPS, TI C6x off the top of my head), still having access to 16 general purpose registers as x86-64 with its up to 16 byte insns.

      2. Load-op insns and many others are split up internally in smaller micro-ops. They are about as useful as assembler macros. Load-op insns are also hurting performance - for example on Intel processors load-op are split on two mops, one of which is dispatched to port 2, which means that two load-ops cannot by dispatched on the same cycle, whereas up to three simple ops can can be dispatched in one cycle.

      3. AVX is good, having the same style for general purpose insns is better.

      4. Dedicated SP engine is a solution to a problem, which does not exist on common RISC architectures anyway. The dependency, which is eliminated by the stack pointer tracker is the dependency of a push/pop insn on that value of SP, which is a result of a previous push/pop. There's no such dependency if simple moves to/from memory (e.g. `movq %rbx, 10(%rsp)') are used as in typical RISC (or in x86 too). Also ARM (and THUMB) can save/restore multiple registers on stack with a single insn, so no dependency there either.

      5. The advantage of 64-bit address space for an architecture, traditionally targeted at embedded and mobile applications is quite dubious.

      x86 has no merits, but just age old quirks, which are solved by throwing in a ton of additional logic and gigahertz. Make no mistake, x86-64 CPUs are good because the manufacturing process is good and not because, but despite the ISA.

    6. Re:Just let x86 die, please. by Anonymous Coward · · Score: 0

      Variable length instruction encoding makes more efficient use of the instruction cache. It is basically code compression, and as such it gives a larger effective ICache size than a fixed length instruction encoding. Even if you have to add marker bits to determine instruction boundaries, it's still a win or at least a wash.

      Modern x86 processors decode instructions before they are cached. i.e. the ICache holds fixed-width instructions like a RISC processor.
      I'll give you the storage benefit on disk and in RAM but, as the meme goes, memory is now very cheap so the compression is unnecessary.

      x86 has load-op instructions. Load-op is a very, very common programming idiom both for hand written assembly and for compiler generated code. ARM and other RISC ISAs require two instructions to accomplish the same thing.

      This isn't a justification, just stating a feature. The all powerful "add eax, [mem_addr]" is a 2-clock instruction that executes as a "mov secret_reg, [mem_addr]; add eax, secret_reg" anyway. There is no benefit to this beyond the previously mentioned "compression". BTW, those directly-from-memory instructions are only important because the x86 has so few registers and, worst of all, those registers are not truly general purpose (look at mul, div, movsb).

      AVX, the new encoding from Intel and AMD, gives you true RISC-like two source, one non-destructive dest instructions.

      This works against you since Atom processors tend to cut back on the big stuff to reduce the die-size. What exactly are you going to do about all the existing software? Or is there a transcoder?
      You're basically saying x86 is superior because Intel is desperately trying to get rid of x86 and replace it with a RISC recoding from the inside out. An efficient RISC architecture which can emulate x86 efficiently would work just as well (IA-64 was both crap and had poor emulation).

      Dedicated stack pointer register allows for push/pop/call/return optimizations to unlink dependence chains from unrelated functions. With a GPR-based stack, RISC has false dependence problems for similar code sequences that they can't really optimize,

      I won't argue the concept but I will point out that SP/ESP/RSP is NOT special. The call/push/pop/leave/ret instructions implicitly reference it, yes, but you can emulate the behavior with other instructions to use any register. That's basically calling convention standardization, unless you're referring to the hardware call rewind stack?

      AMD64 got rid of cruft, added more GPRs, and added modern features like PC-relative addressing modes, removing that advantage from RISC too.

      True. Except layering all that crap on top of the existing crap is a problem because Atom (due to the size-proportional-to-power-used problem) inherently makes it uncompetitive, most Atoms don't even have the 64bit mode at all for this reason. If you are suggesting that the Atom chips should just boot straight into EM64T and remove the 16bit instruction set then I'll buy into that.

      ARM's 64 bit extensions were just announced and won't be shipping until 2014. x86 has been 64 bit for 8 years.

      This is an argument about ARM, not RISC in general. ARM is an architecture that is customised by many licensors, x86 is Intel/AMD. Also, ARM is mostly embedded where 64bit memory addressing is unnecessary, it's only as smartphones have become confused about what a phone is supposed to do that large amounts of RAM are pushing the limits.
      If you want to argue about RISC64, talk about how AMD64 compares to Power (PPC64).

      ---
      If you want a blunt summary of the problems with x86:

      • It's too big, there are too many features, too many different modes of operation, modes that can be recursively active inside other modes
      • It's redundant, there are many instructions that do the same thing. This is a problem for pick
    7. Re:Just let x86 die, please. by TheDarkMaster · · Score: 1

      Well... I will like (and buy) a tablet where I can install and use Paint Shop Pro 7 (yep, is old) without emulation and can use my finger or a stylus to draw, and be capable of using Miranda IM without ugly hacks. Applications my friend, applications.

      P.S: I know that I can have simmilar applications on Android or iPad... But I really, really do not like the idea of "happy walled garden" with pseudoapplications ("apps" in html/javascript? WTF), sorry.

      --
      Religion: The greatest weapon of mass destruction of all time
    8. Re:Just let x86 die, please. by PolygamousRanchKid+ · · Score: 1

      However, that was when I was still a child. Now I'm grown, it's time to put away childish things.

      There is IBM Mainframe System 360 code from the '60s still running on current zEnterprise systems today. That code was probably written while you were still swimming around in your dad's balls (no offense intended; it's just an amusing expression).

      This will also be the case with x86. It will stay around forever, because it has been around forever. Tautology intended.

      However, supporting legacy stuff does not necessarily preclude innovation.

      --
      Schroedinger's Brexit: The UK is both in and out of the EU at the same time!
    9. Re:Just let x86 die, please. by Anonymous Coward · · Score: 0

      I doubt this will succeed anyway, because:

      1. x86 has traditionally dominated because of compatibility with old software. Microsoft could never switch to ARM or none of the existing Windows software would run. Apple managed it (PowerPC->x86), but they don't care about backwards compatibility as much as Microsoft, and they also didn't have much to lose since few people used macs at the time.

      2. Lots of Android software, and all iPhone software is compiled ARM code. Anyone choosing x86 for their Android device would have to accept that lots of software (mostly games) wouldn't run on it.

    10. Re:Just let x86 die, please. by cyber-vandal · · Score: 1

      Tablets are the future apparently. People keep telling me that on here and calling me all sorts of names when I point out all the things that I want from a computer that tablets can't do, like run my software or upgrade the storage or RAM without having to buy a new tablet.

    11. Re:Just let x86 die, please. by JackDW · · Score: 3, Interesting

      Indeed. And the ARM ISA isn't even RISC anyway. In fact, which ARM ISA are we even talking about here? Thumb, Thumb2, ThumbEE, Jazelle or the 32-bit ISA? And which extensions, I wonder? NEON, maybe? Or one of the two different sorts of FPU? That's already a significantly complex instruction decoder. The x86 microcode-for-uncommon-instructions approach is probably better.

      Whenever this topic comes up, the discussion is immediately flooded with ARM fanboys insisting that x86 can never compete for magical reasons that don't stand up to sensible analysis. And as Intel approaches ARM's level of power consumption, as they inevitably must (for there is no magic in ARM and there is nothing physically preventing parity), what we hear is denial: the insistence that Intel is playing dirty tricks.

      At least, post OnLive, nobody is claiming that there is no demand for x86 applications on mobile devices. I suppose the "ARM = magic" power claims will have a similar lifetime, and one day will look as silly as claims that Windows XP will be a failure because everyone will be using Linux by 2005. Hope is a good thing, but this is just foolishness.

      --
      You're an immobile computer, remember?
    12. Re:Just let x86 die, please. by rev0lt · · Score: 1

      The 80286 instruction set was simply god-awful. It was basicly a 8086 with better performance and a castrated and inconsistent protected mode support. You can't write truly cross platform assembly in most of the available RISC processors either. There's always extensions, issues, extra register, hiccups and whatnot.

      Intel has been translating x86 legacy instructions to RISC operands for ages. It happens in almost every major CPU released in the last decade. So, technically, x86 is already gone a long time.

    13. Re:Just let x86 die, please. by AcidPenguin9873 · · Score: 1

      1. Having variable length instructions complicates instruction decoding, which cost die space and cycles (once for actual decoding and once for instructions spanning fetch boundaries). Also several processor architectures save 16-bit instructions (ARM, SH, MIPS, TI C6x off the top of my head), still having access to 16 general purpose registers as x86-64 with its up to 16 byte insns.

      Yes, those are the standard arguments against variable length instructions. But both Intel and AMD use extra marker bits to mark the instruction boundaries, which removes the extra-cycles penalty. I'd argue that the extra area with the marker bits is *still* smaller than wasting area on non-compressed instructions. With the cycle penalty gone, now you're just left with a die size argument for the initial decode hardware and the cross-fetch-boundary hardware. I'll argue that that area cost is absolutely minimal. I also named an advantage: increased performance due to higher ICache hit rate for the same ICache size. I'll take that advantage over the die size disadvantage every time.

      2. Load-op insns and many others are split up internally in smaller micro-ops. They are about as useful as assembler macros. Load-op insns are also hurting performance - for example on Intel processors load-op are split on two mops, one of which is dispatched to port 2, which means that two load-ops cannot by dispatched on the same cycle, whereas up to three simple ops can can be dispatched in one cycle.

      Sandy Bridge and all AMD processors since K7 do it with a single micro-op.

      3. AVX is good, having the same style for general purpose insns is better.

      Good thing AVX is extensible.

      4. Dedicated SP engine is a solution to a problem, which does not exist on common RISC architectures anyway. The dependency, which is eliminated by the stack pointer tracker is the dependency of a push/pop insn on that value of SP, which is a result of a previous push/pop. There's no such dependency if simple moves to/from memory (e.g. `movq %rbx, 10(%rsp)') are used as in typical RISC (or in x86 too). Also ARM (and THUMB) can save/restore multiple registers on stack with a single insn, so no dependency there either.

      RISC still needs to maintain a stack pointer/frame pointer register for function calls. This maintenance, which requires using general purpose instructions like add/sub/mov, is what causes the false dependence. You haven't addressed how to remove this dependence in RISC.

      5. The advantage of 64-bit address space for an architecture, traditionally targeted at embedded and mobile applications is quite dubious.

      ARM has been making a lot of noise about getting into servers. Servers as I understand them today really do want true 64-bit addressing.

      Make no mistake, x86-64 CPUs are good because the manufacturing process is good and not because, but despite the ISA.

      x86 has no merits, but just age old quirks, which are solved by throwing in a ton of additional logic and gigahertz. x86-64 CPUs are good because x86 CPU designers are pretty smart. I would say that x86 ISA has little impact on the quality of the CPU. Likewise, RISC ISA has little to no impact on the quality of the CPU. See this paper for an example.

    14. Re:Just let x86 die, please. by AcidPenguin9873 · · Score: 1

      Modern x86 processors decode instructions before they are cached. i.e. the ICache holds fixed-width instructions like a RISC processor. I'll give you the storage benefit on disk and in RAM but, as the meme goes, memory is now very cheap so the compression is unnecessary.

      You are talking about a micro-op cache, and not all x86 processors have one. Sandy Bridge does, but it *also* has a regular old ICache which holds raw instruction bytes. And I'm not talking about disk or RAM, I'm talking about the on chip L1 SRAM. Bigger effective ICache == fewer cache misses == better performance.

      This isn't a justification, just stating a feature. The all powerful "add eax, [mem_addr]" is a 2-clock instruction that executes as a "mov secret_reg, [mem_addr]; add eax, secret_reg" anyway. There is no benefit to this beyond the previously mentioned "compression". BTW, those directly-from-memory instructions are only important because the x86 has so few registers and, worst of all, those registers are not truly general purpose (look at mul, div, movsb).

      Sandy Bridge and AMD processors since K7 have done it with one micro-op. With renamed registers it's not that difficult to do. And load-op is more useful than just for compensating for lack of GPRs. For example, matrix-multiplication, SHA hashing, basically anything that does processing of a huge stream of data.

      This works against you since Atom processors tend to cut back on the big stuff to reduce the die-size. What exactly are you going to do about all the existing software? Or is there a transcoder? You're basically saying x86 is superior because Intel is desperately trying to get rid of x86 and replace it with a RISC recoding from the inside out. An efficient RISC architecture which can emulate x86 efficiently would work just as well (IA-64 was both crap and had poor emulation).

      I was listing reasons that x86 was superior, *or at least on par with*, any given RISC ISA. AVX gives you the same instructions for fewer prefix bytes, and adds an additional register field to allow for 3 opera d encoding (2-src, 1 dest). It's not a wholesale replacement of x86.

      I won't argue the concept but I will point out that SP/ESP/RSP is NOT special. The call/push/pop/leave/ret instructions implicitly reference it, yes, but you can emulate the behavior with other instructions to use any register. That's basically calling convention standardization, unless you're referring to the hardware call rewind stack?

      That is exactly the problem I'm talking about. When you emulate your stack with a GPR, it looks like you have a long, serial chain of function calls, parameter passing, returns, another call following the first call/ret, etc. x86 processors, by virtue of their dedicated stack pointer register, have had optimizations for years (since the Pentium M) which track the call/ret/push/pop increment and decrements in a sideband structure and don't actually touch the stack pointer register itself. That allows independent, out-of-order execution of independent code sequences that GPR-based stack architectures don't have.

      True. Except layering all that crap on top of the existing crap is a problem because Atom (due to the size-proportional-to-power-used problem) inherently makes it uncompetitive, most Atoms don't even have the 64bit mode at all for this reason. If you are suggesting that the Atom chips should just boot straight into EM64T and remove the 16bit instruction set then I'll buy into that.

      The die size penalty for supporting the legacy modes and instructions is so minimal compared to the cache sizes and queue sizes of modern processors that it's not worth basing an argument on it.

      This is an argument about ARM, not RISC in general. ARM is an architecture that is customised by many licensors, x86 is Intel/AMD. Also, ARM is mostly embedded where 64bit memory addressing is unn

    15. Re:Just let x86 die, please. by Anonymous Coward · · Score: 1

      Whenever this topic comes up, the discussion is immediately flooded with ARM fanboys insisting that x86 can never compete for magical reasons that don't stand up to sensible analysis.

      I don't give a fuck if the reasons are "magic", when the mightiest semiconductor giant on ghod's green earth can't bring their own architecture up to match everybody and their brother making ARMs (usually a node behind -- see "mightiest semiconductor giant"), the only fanboys I see are the ones denying observable reality and claiming x86 is just as good. If it's so good, then why in hell do all current ARMs beat all current x86es so soundly?

      And as Intel approaches ARM's level of power consumption,

      But Intel just isn't approaching ARM's power consumption -- Intel has a single-core x86 SoC that idles at 2.8W (and they think they can get it down to 2W for production, which is not unbelievable), while all the competing multicore ARM SoCs get comparable performance* with less than 1W peak power, and 10s of mW idle. For the sake of argument, I'll say that single-thread benchmark is in fact representative of typical workloads, or hell, suppose it favors the ARM, such that Medfield is beating ARM by a factor of 2 in the real world -- it's still 100 times more idle power, and 3x the peak power, for merely double the performance. How the hell do you explain that away?!

      *Yes, I'm aware the single-core Medfield seems to soundly beat its multi-core ARM competitors -- on a single-thread benchmark. Now ain't that the sort of stat fanboys love?

      as they inevitably must (for there is no magic in ARM and there is nothing physically preventing parity), what we hear is denial: the insistence that Intel is playing dirty tricks.

      My point exactly! Again, granted there's nothing magical about ARM, why the hell don't they have real, inarguable parity? Even their claimed specs (and I'm willing to believe there's no "dirty tricks", just the usual bias where nobody leaks a benchmark that makes them look bad) simply don't support any claim of parity. (Yet you keep making it... Who's the fanboy again?) It sure seems like there's something magical -- maybe it's not ARM blessed with magical power efficiency, but x86 is cursed with magical suckage? That, or Intel has turned it's CPU design work over to slightly educated baboons -- there's no other logical explanation I can see for the concrete reality.

    16. Re:Just let x86 die, please. by Guy+Harris · · Score: 1

      Perhaps create an instruction set that lets you get more out of your MFG process; Maybe one that's cross platform (like ARM is).

      What do you mean when you say the ARM instruction set is "cross platform"?

      Let's look at THAT problem and solve it with perhaps a new type of linker that turns object code into the proper machine code for the system during installation (sort of like how Android does).

      Or how the IBM System/38 and successors do it (compilers generate a very CISCy high-level virtual instruction set; core OS code translates it to machine code when it's first run). ("How Android does" is, I think, pretty much "how Java does".)

    17. Re:Just let x86 die, please. by Guy+Harris · · Score: 2

      I scoured your post for one actual reason why you think x86 is an inferior ISA, but I couldn't find any. I'll give you a couple reasons why it is superior, or at least on par with, any given RISC ISA, on its own merits, not taking into account any backwards compatibility issues:

      • Variable length instruction encoding makes more efficient use of the instruction cache. It is basically code compression...
      • x86 has load-op instructions. Load-op is a very, very common programming idiom both for hand written assembly and for compiler generated code. ARM and other RISC ISAs require two instructions to accomplish the same thing.

      The latter pretty much amounts to "code compression"; maybe assembler-language programmers would also find it convenient, but compilers probably don't really care much, except for a little extra register pressure.

      • Dedicated stack pointer register allows for push/pop/call/return optimizations to unlink dependence chains from unrelated functions. With a GPR-based stack, RISC has false dependence problems for similar code sequences that they can't really optimize,

      x86 has some instructions that use one of the GPRs - ESP/RSP - specially. RISC processors have calling conventions that use one of the GPRs specially. What exactly are the differences here?

    18. Re:Just let x86 die, please. by Guy+Harris · · Score: 1

      There is IBM Mainframe System 360 code from the '60s still running on current zEnterprise systems today.

      ...and the latest implementations of it use the same "translate some multi-step instructions into internal micro-ops" technique that a lot of x86 processors, dating back to the Pentium Pro, do. (They also use Alpha's "trap some instructions to processor-dependent code running in a special mode with access to some special internal registers" technique, only they call it "millicode" rather than "PALcode" - and they have some more instructions to trap.)

    19. Re:Just let x86 die, please. by Anonymous Coward · · Score: 0

      • x86 has load-op instructions. Load-op is a very, very common programming idiom both for hand written assembly and for compiler generated code. ARM and other RISC ISAs require two instructions to accomplish the same thing.

      I'm curious, is the x86 load op a single cycle instruction or did you only mean that it saves cache space?

      x86 certainly can compete very well against RISC ISA, but x86 has had immense amounts of money sunk into the design, and ARM only started recently due to programmable SoC invading every single appliance. While I haven't seen any, I wouldn't be surprised if someone had made a Toaster with a ARM SoC.

      It's an interesting playing field, and there's even some interesting MIPS cores coming out now from Broadcom and Ingenic. I only hope someone makes a inexpensive reasonably powerful (~1GHz) MIPS development board like the Snowball or Pandaboard.

    20. Re:Just let x86 die, please. by Archibald+Buttle · · Score: 1

      The thing that prevents Intel from approaching ARM levels of power consumption is transistor count. Transistors consume power. If your chip demands more active transistors to operate it will use more power.

      ARM processor cores simply require far fewer transistors than an Intel core. The phenomenally complex Intel instruction set necessitates this, and cannot be avoided without removing backward compatibility. In order to reduce the active transistor counts complex designs can be used to aggressively disable parts of the core that are not in use - although this technique for power reduction is also used by ARM too.

      Intel's only remaining option of making their chips power competitive with ARM is to use smaller manufacturing processes, since smaller transistors require less power. ARM-based competitors to Intel chips are often two, if not three, generations of manufacturing process behind. Obviously this is not a situation that Intel can count on remaining the same forever.

    21. Re:Just let x86 die, please. by JackDW · · Score: 1

      I've heard this before, and sorry, I'm not convinced. I can argue that ARM's ISA is just as complex and crufty as x86, what with multiple ISAs, heaps of extensions, and features that must have seemed like a good idea at the time. It's cursed with the same problems you wrongly imagine to be x86-exclusive. If you really wanted to design an ISA to minimise energy use and eliminate all need for backwards compatibility, then you certainly could, but it wouldn't be much like ARM, which was intended as a high-performance ISA when it was developed in the mid 1980s (contemporaneously with 386, I might add).

      Anyway, most of the "active" transistors in an x86 or ARM core are cache.

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  15. Snore... Ketchup. by Anonymous Coward · · Score: 0

    Wake me when Intel releases a product I want. This part is going to be obsolete by the time the next iPad comes out.

    What Intel needs to figure out is how to put 8GB of ram, x86-64, quadcores and then make it use 1 watt. Bonus is to figure out how to turn OFF the unused RAM by coming with a process that doesn't need to be refreshed. Then we'll see a chip that is competative to ARM design.
    Intel's failure is that they aren't reducing TDP in any of their chips, rather it keeps increasing, this unfortunately has the problem of hitting the wall. Already you can only put 8 CPU's in a 15A rack. The TDP needs to come down for real, not with marketing.

    I don't know what Intel is shooting for here. If they are shooting for the Tablet, it will be obsolete shortly with those specs. Current desktops are 8GB ram 64bit and quadcore as standard. Putting anything out there that is less, even for a "tablet" is just admitting they can't put a desktop experience in a tablet. This is where Apple figured out the right thing to do... pick a better power conserving CPU and then don't try to put the desktop on the tablet. Sure it is essentially the same OS, but by not putting the MacOS UI on it and instead coming up with something more stripped down that doesn't rely on any other unused libraries (think about why Windows is bloated... the same OS is used for the Server and Desktops.) And no development tools on the device it sellf (See *nix land)

    Microsoft's entire screwup dates back to trying to integrate MSIE into the system too rigidly. Had they not tied it down to the OS and instead broke it accross componets that could be swapped out, we might not be were we are today with 2.5 competing alternatives. So the Server OS (NT) got spitpolished up and became Windows 2000, XP, Vista and 7, heading clear in the opposite direction of a lightweight GUI on top of DOS that ended in WindowsME. Meanwhile Microsoft botched WindowsCE/Mobile/Phone, several times. CE should have started out as a stripped down NT (as in figuring out how much to strip out of NT to make it work on embedded devices.) Instead Microsoft had to duplicate efforts countless times, ending with everyone dumping their PDA's (the predecessor to the Tablet.)

    We have already seen Microsoft fail at the Tablet environment already, and we've seen why (OEM's produce throwaway expensive crap) Exactly what is happening on Android. Android's future is Windows Mobile 5's past already. The OEM's need to shape up and produce better hardware with the same user experience on the same OS. We've seen this game before with the CDi, 3DO, WindowsCE/Mobile, and even Palm. The OEM's produce inferior hardware and nobody wants to develop for it (except for some hardcore nerds) , the end users end up stuck with the bloatware that comes with the phones and tablet and never buy anything from the market because their brand new device doesn't run the current version of the OS.

    Only would a mobile phone company have the gall to force it's users to throw away their product and purchase a new one within the warranty period to get the latest software. This is what the WindowsMobile OEM's were doing before. I've been burned there, I'm not getting burned again with Android. When I see a OEM support their tablet for 6 years (like a game console) I'll consider that brand as good. Till then, screw them all and let the grandmas use them for portable throwaway web browsers.

    1. Re:Snore... Ketchup. by oakgrove · · Score: 1

      Exactly what is happening on Android. Android's future is Windows Mobile 5's past already.

      As a current user of Ice Cream Sandwich on a Motorola Xoom, you sir are quite wrong. What Android tablets needed was good software. That software is here.

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  16. Huh? by Anonymous Coward · · Score: 0

    Typical ARM-based SoC have idle power around 50-200mW, 2W ain't going to cut it.

  17. Dubious by A12m0v · · Score: 1

    Intel will need to bend the law of physics before their power hungry chips can match the the energy efficiency of ARM SoCs, but if anyone can do it it'll be Intel. Intel took x86 to workstations and supercomputers killing many RISC processors in the process. It'll be fun to see them pull it off again against ARM.

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    1. Re:Dubious by ArcherB · · Score: 4, Insightful

      Intel took x86 to workstations and supercomputers killing many RISC processors in the process. It'll be fun to see them pull it off again against ARM.

      No, it wouldn't. RISC is a superior instruction set. x86 only beat RISC because it was really the only game in town if you want to run Windows, which every non-mac user did. At the time, the desktop was king and made Intel lots and lots of money, which they used to beef up their server offerings. Now we are stuck with x86 with RISC being used only in "closed" architectures like smart phones, consoles and big-iron servers.

      I like competition. I'd rather see ARM make gobs of money of designing chips that everyone can improve on than Intel make gobs and more gobs of money selling desktop, server and mobile chips that only they may design, produce and sell.

      The final processor line that Intel makes will be the one they are producing when they become the only game in town.

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    2. Re:Dubious by the+linux+geek · · Score: 2, Informative

      Every Windows release from the NT line since NT 3.1 has run on at least one RISC architecture.

    3. Re:Dubious by Runaway1956 · · Score: 4, Interesting

      Bloodthirsty bastard, aren't you? Killing off the competition is fun?

      I haven't liked Intel very much since I read the first story of unethical business practices. Intel doesn't rank as highly on my shitlist as Microsoft, but they are on it.

      --
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    4. Re:Dubious by Anonymous Coward · · Score: 1

      > Now we are stuck with x86 with RISC being used only in "closed" architectures
      > like smart phones, consoles and big-iron servers.

      Every x86 chip since the Pentium Pro has had a RISC core.

      The x86 CISC is just a wrapper around that.

    5. Re:Dubious by SpinyNorman · · Score: 4, Interesting

      RISC isn't an instruction set - it's a design strategy.

      RISC = reduced instruction set computing
      CISC = complex instruction set computing

      The idea of RISC (have a small highly regular/orthogal instruction set) goes back to the early days of computing when chip design and compiler design wasn't what it is today. The idea was that a small simple instruction would correspond to a simpler chip design that could be clocked faster than a CISC design while at the same time being easier to compile optimized code.

      Nowadays advances in chip design and compiler code generation/optimization have essentially undone these benefits of RISC, but the remaining benefits are that RISC chips have small die sizes hence low power requirements, high production yields and low cost, and these are the real reasons ARM is so successful, not the fact that the instruction set is "better".

    6. Re:Dubious by Henriok · · Score: 3, Insightful

      What RISC platform did XP, Vista and Windows 7 run on? XP had support for Itanium, but that's not a RISC platform. Vista and Win7 only support 32- and 64-bit x86. So.. It seems you are wrong in your statement.

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    7. Re:Dubious by GennarinoParsifalle · · Score: 1

      Windows NT used to support MIPS R3000 and R4000 and Alpha processors from Digital (both RISCs). Wikipedia page claims also PowerPC and RISC support but I never saw personally any of the two ports.

    8. Re:Dubious by Anonymous Coward · · Score: 0

      Microsofts Xbox-360 runs a Win NT kernel, and the X-box360 uses a triple-core PowerPC processor, so Microsoft is still developing a PowerPC build of their software.

    9. Re:Dubious by abainbridge · · Score: 3, Interesting

      > RISC is a superior instruction set. x86 only beat RISC because it was really the only game in town if you want to run Windows

      Modern ARM processors aren't pure RISC processors. Most ARM code is written in Thumb-2, which is a variable length instruction code just like x86. Back in the 90s when transistor budgets were tiny, RISC was a win. When you only have a hundred thousand gates to play with, you're best off spending them on a simple pipelined execution unit. The downsides of RISC has always been the increased size of the program code and reduced freedom to access data efficiently (ie with unaligned accesses, byte addressing and powerful address offset instructions). With modern transistor budgets it is worth spending some gates to make the processor understand a compact and powerful instruction set. That way you save more gates in the rest of the computer than you spend doing this (ie in the caches, databuses and RAMs).

      As a result of all this, in some ways, ARM chips are evolving to look more and more like an Intel x86 design. I'm still a big fan of ARM though. Intel will have a long way to go to compete on price, even if they can compete on power.

    10. Re:Dubious by Anonymous Coward · · Score: 0

      Yes, but the apps where mostly x86 run with FX!32, running slower than on cheaper x86.

    11. Re:Dubious by eugene2k · · Score: 1

      The GP isn't talking about the NT line though (even though we're talking about the NT line here). In other words it's a reading comprehension problem.

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    12. Re:Dubious by eugene2k · · Score: 1

      But that's not the problem of the OS, it's a problem of the RISC platforms, since the OS was identical on x86 as well as on RISC platforms, if the apps were mostly made for x86 it shows that RISC wasn't as superior as the OP claims.

      --
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    13. Re:Dubious by zefrer · · Score: 1

      Not this again.. It doesn't matter that it is superior, and I'm not saying it's not, because all current CISC based CPUs translate their instructions into RISC before executing, making them indistinguishable, performance wise, from purely RISC based designs.

      Fact is there are no purely CISC based designs anymore, haven't been any for more than a decade now, and perpetuating the myth that x86 is CISC and is slower than RISC helps no one.

    14. Re:Dubious by rev0lt · · Score: 1

      ...And x86 was a lot cheaper and easier to license (Amd, Cyrix, TTI, etc). And the software offer was vastly superior. But the funny thing is, Intel did have RISC processors (i860 and i960), and they were quite popular as general-purpose cpu's. Most modern Intel cpus _are_ RISC, as they translate CISC instructions to what they call "micro-ops" (internal RISC instructions), so the line between x86/CISC and RISC design has been blurred at least since the old Pentium II.

    15. Re:Dubious by AJH16 · · Score: 1

      Perhaps you could explain this since you seem to be one of the most level headed posters. I work on the software side of the IT house with a fair bit of knowledge in to the electron pushing side, but only in so far as it is necessary for software development, but I've never understood the RISC is better argument. From a purely software implementation standpoint, I've almost universally ended up with significantly faster execution on x86 (and particularly x64) than with anything ARM based, even at similar clock frequencies.

      From a developer's mindset, it seems like this should be the case too since a CISC gives you more optimized targets to hit for assembly calls provided your compiler and software design are optimized to be able to use them. The obvious primary concern would simply be price and if the added complexity resulted in a slower number of effective operations per second, but that hasn't seemed to be that significant, at least as long as I've been in that level of the game. (Again, talking purely from a software developer's viewpoint.)

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    16. Re:Dubious by hairyfeet · · Score: 1

      "Everyone go to hell except cave 76!" sorry to steal from Mel Brooks but fanbois like you just make me think of that bit. Frankly ARM sucks on instructions per cycle and simply can't do the amount of work even a CULV Intel or AMD chip can without blowing their power advantage all to shit. That is why you don't see anybody in the top 10 supercomputers running ARM chips, its a cell phone and embedded chip and simply wasn't built for real performance.

      X86 frankly stomps ARM in performance, ARM stomps X86 when all you care about is power consumption like in say a smartphone. Personally I like the way AMD is going about it with Bobcat where you use a simpler X86 core paired with a more powerful GPU but since i use and work with media a lot maybe that's just me. But thinking ARM is gonna take over the world is frankly more than a little delusional as by the time you ramp it up to the level of performance of even a Core2Quad or Phenom II you've blown any advantage you had for running ARM in the first place.

      Finally if you think desktops and laptops are going anywhere I have a lovely bridge you may be interested in. The reason PC sales have slowed is actually quite simple and doesn't have a damned thing to do with ARM, it has to do with the fact that X86 chips have become so insanely overpowered that they passed "good enough" for the jobs the masses have several years ago and people have more computers than they can use. In my own family we are up to 6 desktops and 3 laptops for a family of four, my boys are playing games on Pentium D desktops and with a $50 HD4850 a piece they are able to play at 1600x900 (native for their 20 inchers) and still have plenty of purty, so why buy new machines? ARM sells because its a disposable unit and if you don't believe that just ask around and see how many people you know have drawers full of old cell phones. Contract is up, old phone is shitcanned and new phone is used. It doesn't have a damned thing to do with advancements of ARM and everything to do with carrier contracts.

      TL:DR? ARM is for cell phones and embedded, x86 is for desktop and laptops and servers that have to do lots of number crunching. If you think ARM has a chance in hell of getting rid of x86 you are totally batshit but if Intel can get the power low enough X86 could easily trump ARM on performance.

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    17. Re:Dubious by godefroi · · Score: 1

      Uh, the GP most certainly IS talking about the NT line:

      Every Windows release from the NT line

      XP, Vista and Windows 7

      I agree, reading comprehension fail. Windows NT DID run on MIPS and DEC Alpha, and I've heard rumours that every release since has had a supported RISC HAL, even though it was never available to the public. I don't have any actual information to indicate that's true, however.

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    18. Re:Dubious by TheRaven64 · · Score: 2

      Everyone says this, but really, CISC is more efficient. CISC code is more compact than RISC code, which helps cache hit rates. Additionally, the most used opcodes tend to be the shortest.

      Actually, this is the everyone-says-it-but-it's-wrong thing. At least, when the RISC in question is ARM. Most 32-bit ARM instructions are 16-bits in Thumb-2 (ARMv8 doesn't have a Thumb mode yet, so all 64-bit instructions are 32 bits). Even without using Thumb-2, I find I get about the same instruction density for both hand-written and compiler-generated assembly for ARM and x86, often with ARM code being 5-10% smaller.

      For example, ARM code supports predicated instructions so a simple if statement can be just a single predicated instruction on ARM while it would need to be a branch on x86. ARM addressing modes are also very rich, which was the place where CISC usually won a lot over RISC. Things like computing the address of an array or structure element can be half a dozen instructions on a traditional RISC architecture, but just one on ARM (x86 is almost as good, but seems to have a lot of addressing modes for things you don't use and, until x86-64, miss a lot of ones that you did want).

      But, more importantly, ARM instruction encodings are very simple. Decoding the opcode is just a mask, as is selecting the registers. This means that the die area used by the instruction decoder is much smaller. This is really important in low power applications, because execution units can employ all sorts of power saving techniques when they're not in use, but the instruction decoder is always on and always in use (except on the Xeons, where micro-ops are cached in loops, but the micro-op decoder in the Xeon is about as complex as the real instruction decoder in an ARM chip so that doesn't actually save anything relative to ARM).

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    19. Re:Dubious by Vijaysj · · Score: 1

      It has been speculated for a long time (I have been hearing it atleast since 2007) That Atom will match the power consumption of ARM in 2012 timeframe. The world (and Intel) knew for a long time that the platform for next generation computing is handheld devices. Intel required time for course correction to intersect this reality and the above data Indicates that the intersection is happening at the tipping point when the entire world is going gaga over smartphones and tablets. It is inevitable that either Medfield or some future architecture will achieve parity with ARM. The question today should be what does the Industry want? For an ARM based architecture I have today SoC's from TI, Nvidia, Qualcomm, Samsung, BRCM etc. Do I want the PC era wintel monopoly for the tablet era? The refrain till recently was that the wintel monopoly will succeed in the mobile era due to the portability of the application built for X86 architecture on windows platform. In todays world of google marketplace and apple appstore I am not sure to what extend this argument holds true.

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    20. Re:Dubious by mikael · · Score: 1

      The problem is that for all commercial developers and businesses, it's not simply a matter of whether that OS is available on that platform, it is whether it is profitable to pay staff to support that platform.

      There were plenty of RISC chips in the 1990's, DEC Alpha, Sun SPARC, SGI/MIPS, each with their own UNIX variant OS. Once Windows NT came onto the market, and starting cutting away at "UNIX prices", it wasn't possible for application developers to justify supporting niche markets with only a handful customers, so they dumped supporting that OS.

      With declining customers and application developers, that forced the workstation vendors to sell out to Microsoft and dump their OS in exchange for Windows NT. In the end these hardware companies just became "box packaging companies" where they took PC components, put them in PC chassis, added an Intel CPU along with Windows OS and manuals, and ended up competing against Dell.

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    21. Re:Dubious by abainbridge · · Score: 2

      Before a typical workstation class CPUs had evolved complex instruction sets. There had not been enough focus on measuring the frequency of use of the various features of the instruction set. When people started analyzing this (ie Patterson and Hennessy) they showed that the vast majority of software spent its time executing code from a tiny fraction of the instruction set. Obviously if you make those common instructions execute much faster, you can afford to remove the rarely used instructions and make the compiler generate a few simpler instructions in their place. Once these complex instructions were removed, it became easier to implement a well balanced instruction pipeline on a single chip. This was a big win. The ARM2 achieved 4 MIPS @ 8 MHz. Compared to a Motorola 68000 which was about 0.6 MIPS at 8 MHz. The chips were a similar cost in 1987. You could have got comparable performance from a 386 at that time, but it would have been much more expensive.

      I'm not entirely sure why contemporary CISC designs failed to achieve good pipelining. I suspect that _correctly_ implementing a CISC instruction set back then was difficult even without considering performance. The digital design tools and methods of the time were very hard to use. Removing most of the instruction set freed up the digital designer's head so they could concentrate on performance.

      By the 2000s though, it was perfectly possible to implement a pipelined CISC processor. One way to do this is to implement a RISC core with a front end that translates CISC instructions into RISC ones. This is what Intel did. The number of gates in the translation logic is significant, but nothing like as large as the number in the L1 and L2 caches that are integrated onto the die these days. The code density in x86 instructions is probably 25% better than a typical RISC instruction set. Therefore you can make the program caches 25% smaller. You probably save enough gates doing that as it cost to implement the translation logic. Another nice advantage of the translation layer is you can change the design of the RISC core whenever you like and no software needs to be ported to the new design.

      My day job is R&D on the Kalimba DSP core used in various SOCs designed by Cambridge Silicon Radio. We've just added a translation layer front end to the core to implement a more CISC like instruction set. This improves code density by over 30% and therefore reduces the program ROM on the SOC by 30%. This reduces the overall cost of the SOC. And there's no performance penalty. For DSP like tasks our core is 2-10x higher performance per dollar and per watt than competing ARM designs.

      My prediction is that ARM will hold on to the mobile market no matter how hard Intel try. Intel's fabs cost too much to run. TSMC do a much better job. I predict that ARM will gradually take the server and desktop market away from Intel.

    22. Re:Dubious by AJH16 · · Score: 1

      Thanks for that great write up. That made a lot of sense and kind of confirmed what my initial guess was. (That a lot of the issues early on were probably related to poor compiler behavior (or perhaps poor instruction choice), since the instructions were not getting well used.) It also gave a lot of accessible insights from a software developer's perspective. I'd agree that Intel would have to get their fab costs down to compete with ARM plus I get the feeling a lot of the manufacturers like being able to make their own die to add features as necessary. That's always going to give a power advantage I'd think if you can put more on the die.

      It will be interesting to see what happens in the server and desktop market, but for the moment, I think that Intel will keep a hold there due to how entrenched x86 is. (People simply won't want to have to get new software.) The one thing that could change that is if the ARM based Windows 8 takes off, but I personally have my doubts about tablet style computing supplanting the traditional desktop, but rather see it emerging as a parallel branch where ARM will dominate.

      --
      AJ Henderson
    23. Re:Dubious by Guy+Harris · · Score: 1

      The downsides of RISC has always been the increased size of the program code and reduced freedom to access data efficiently (ie with unaligned accesses,

      Which, as far as I know, at least one RISCs supports in recent implementations (Power Architecture). SPARC doesn't have it, and I think ARM didn't have it at least at one point.

      byte addressing

      If you mean "as opposed to word addressing", as far as I know, all the major RISCs used in general-purpose computing are byte-addressed. Alpha was a little weird, at least until the BWX (Byte/Word eXtension) instructions were added, but the others had/have byte and 2-byte loads and stores.

      and powerful address offset instructions

      Do you mean "more complex addressing modes" here? (Presumably you aren't referring to auto-increment and auto-decrement and so on, as they're pretty much dead; I seem to remember Andy Glew in comp.arch saying that they made pipelining harder, so Intel was in a better position to speed x86's up than Motorola were in to speed up 68k's.)

    24. Re:Dubious by the+linux+geek · · Score: 1

      How is Itanium not RISC? It's fixed-length and load-store, which is the conventional definition of "RISC." There's no real difference between VLIW-as-implemented-by-IA64 and a conventional superscalar in-order RISC with parallelism hints, and this is coming from someone who's been doing Itanium assembly language for a few years. Vista and Windows 7 continue supporting IA64 in their server versions.

    25. Re:Dubious by shadesOG · · Score: 1

      Internally Intel's chips break down x86 CISC instructions to RISC micro-operations. So essentially x86 is now RISC.

    26. Re:Dubious by marnues · · Score: 1

      brokeninside certainly gives the theoretical reasons, but in truth there are no such things as CISC and RISC anymore. RISC was developed because someone back in the 80s realised that the complex instructions of x86 and the like were not only slowing down the system, they were also useless. In theory RISC vs CISC should have been a trade-off between simple instructions that run quickly versus well packed instructions that perform several tasks in one much slower cycle. However, it turned out that the trade-off was nonexistent. The complex instructions were too specific for compilers and higher order languages to use, so the vast majority of code was effectively running RISC operations on CISC platforms. So Intel being the thinkers they are changed everything when they introduced a RISC-like architecture with extensive microcoding to make it's CISC instruction set work up to snuff. Calling Intel a CISC architecture is like calling Russia Communist. And since the RISC architectures have incorporated multiplication and other instructions that don't fit neatly into RISC theory, there isn't a true RISC archictecture out there.

      CISC vs RISC was a paradigm shift, not an ongoing debate.

    27. Re:Dubious by JohnnyBGod · · Score: 1

      XP is NT 5.1, Vista is NT 6, 7 is NT 7.

  18. Re:whoosh...you missed... by Svartalf · · Score: 1

    Recent track record... Yeah, sure...

    http://www.pcper.com/reviews/Graphics-Cards/Larrabee-canceled-Intel-concedes-discrete-graphics-NVIDIA-AMDfor-now

    There's a few others like this one. This includes the GMA stuff where they claimed the Xy000 series of GMA's were capable of playing games, etc. They're better than their last passes at IGPs, but compared to AMD's lineup in that same space, they're below sub-par. Chipzilla rolls out stuff like this all the time. Been doing it for years now.

    Larrabee.
    Sandy Bridge (at it's beginnings...).
    GMA X-series.
    Pentium 4's NetBurst.
    iAPX 432.

    There's a past track record that implies your faith in this is a bit misplaced at this time.

    --
    I am not merely a "consumer" or a "taxpayer". I am a Citizen of the State of Texas
  19. The past stays with us by Weaselmancer · · Score: 1

    We still use Imperial units in the US. And do you remember the shortage of competent Cobol programmers back when Y2K was the big worry?

    The world does indeed move on, but the past stays with us for a long while. A low power x86 SOC is still a useful and a wonderful thing.

    My first thought when I read the article was "Cool! You'll be able to get a notepad to run WINE and native Windows XP now!" I can see TONS of uses for this, even with the lousy power specs. Industrial/business types don't like to let go of legacy systems. I just know I'm going to get some work someday that this chip will be the perfect fit for. I'm thrilled. Excellent work Intel.

    Is ARM better? In this marketspace, absolutely. It's the best forward thinking decision you could make. But not everyone looks forward or is willing to spend cash on rewriting some legacy system. This chip fits a need perfectly.

    --
    Weaselmancer
    rediculous.
  20. I'll believe it when I see it by peppepz · · Score: 1
    We already had sensationalist press reports about how Intel would displace ARM thanks to the Moorestown chips, that would let us run the unmodified World of Warcraft on our phones, and so on. Result in reality: zero devices using Moorestown shipped.

    Somebody will also remember how Larrabee was meant to smother the market of video cards, the rumors that Sony was to build the PS4 upon it, etc. Result in reality: Larrabee shelved.

    It's easy for Intel to beat ARM in performance benchmarks - they have been doing this since the beginning. The point is, that they have to beat ARM in power efficiency, and it looks like Medfield isn't quite there yet.

  21. Intel's process tech is the best by Dr.+Spork · · Score: 1

    If this thing can compete on performance with ARM chips, it's only because Intel can make miracles happen in silicon. Of course, we might never know what would happen if Intel used their latest process technology to print ARM chips like Apple's A6 or whatever the next generation will be. But it would be very good.

  22. Meego lives? by Anonymous Coward · · Score: 0

    I wonder if this means Meego will finally get the last push it needs to be allowed onto the market. The chips, I could not care less about.

  23. "Benchmark-wise"? by Anonymous Coward · · Score: 0

    I Think Not. Really, this shouldn't need to be said, but apparently the submitter is clueless here. You can't presume proof before you have it, thanks. That means no claims about benchmarks without the benchmark numbers (and all the details, dammit, the numbers are useless enough as it is) in hand. Say the specs make you expect it will out-perform the competition, fine. But putting it like this is vaguely handwaving with extreme presumption. Techies really ought to know better than deploying marketeers' weasel word salad, thanks.

  24. Performance per watt by jones_supa · · Score: 1

    So...how's the performance per watt if we compare these recent ARM and Intel offerings?

    I was also thinking that the Atoms probably have more all sorts of acceleration units. I'm not sure how important would those be on a tablet or a phone though. Anyway, there was an interesting discussion pondering if it would be possible to run Folding@Home on a phone. It ended by realizing that the ARMs wouldn't have the same kind of FPU power.

  25. MIPS and ARM by brokeninside · · Score: 1

    Admittedly, _released_ versions of Windows 7 and Windows Vista didn't support any RISC chips. The days of NT shipping with install discs for multiple architectures are long gone.

    But the the most recent versions of the Windows family still supports RISC chips, just on a different code branch (Windows CE/Mobile/Pocket PC/Whatever they're calling it these days). Microsoft had planned on re-unifying the branches with Windows 7 but that goal got pushed back to Windows 8.

  26. ARM is now using 28nm fab processing by tyrione · · Score: 1

    Perhaps everyone is too stoned from Christmas but 28nm stamping is already approved with GlobalFoundries, TSMC and Samsung.

    http://arm.com/about/newsroom/globalfoundries-and-arm-deliver-optimized-soc-solution-based-on-arm-cortex-a-series-processors.php

    http://www.tsmc.com/tsmcdotcom/PRListingNewsArchivesAction.do?action=detail&newsid=6181&language=E

    http://www.samsung.com/global/business/semiconductor/newsView.do?news_id=1254

  27. RISC, CISC & VLIW by unixisc · · Score: 2

    Intel took x86 to workstations and supercomputers killing many RISC processors in the process. It'll be fun to see them pull it off again against ARM.

    No, it wouldn't. RISC is a superior instruction set. x86 only beat RISC because it was really the only game in town if you want to run Windows, which every non-mac user did. At the time, the desktop was king and made Intel lots and lots of money, which they used to beef up their server offerings. Now we are stuck with x86 with RISC being used only in "closed" architectures like smart phones, consoles and big-iron servers.

    I like competition. I'd rather see ARM make gobs of money of designing chips that everyone can improve on than Intel make gobs and more gobs of money selling desktop, server and mobile chips that only they may design, produce and sell.

    The final processor line that Intel makes will be the one they are producing when they become the only game in town.

    I fully agree. Not only is RISC superior to CISC, it's even turned out to be more optimal than VLIW. After all, remember all the hype about VLIW when Intel & HP first started working on the Itanium? It turned out that that the dynamic analysis part of RISC CPUs that Itanium was going to move into the Compiler, such as branch prediction, register renaming, etc, was just a small portion of the Si, so not much was really saved in terms of real estate there. In the meantime, the much ballyhooed VLIW compilers were all but impossible to write, so that in the end, the advantages of Itanium were minimal. Besides, a lot of the advantages that EPIC really brought, such as large scale parallelism, was implemented successfully in the last Alpha 21364 processor, as well as later POWER processors. In short, there was nothing that VLIW could do well enough to give it the sort of advantage over RISC that RISC had over CISC, or most specifically, the x86 platforms.

    However, Intel did manage to knock off RISC by successfully pushing the Itanium vaporware and causing Compaq & HP to end the Alpha & PA-RISC CPUs and migrate to the Itanium. Two of the best CPUs that the industry had were thereby lost. Aside from that, Microsoft played its role in destroying the potential of RISC by systematically ignoring the RISC versions of NT: if Microsoft had ported every, or even the most used Windows applications of Microsoft to the Alpha, or the MIPS, all the companies that based themselves on that - Carrerra, Aspen, Microway, DeskStation, NeTpower, et al would have been pretty successful computer vendors. That is the reason that Intel could catch up w/ RISC - Microsoft did not bother to make RISC versions of NT as successful as Wintel.

    Given Intel's fiasco w/ the Itanium, I doubt that they'll dare venture into new adventures w/ new CPU platforms anytime soon. Even X-Scale was not such a success, was it?

    1. Re:RISC, CISC & VLIW by godefroi · · Score: 1

      Even X-Scale was not such a success, was it?

      You know X-Scale was ARMv5, right? Intel was not blazing new trails there. They got the StrongARM technology from DEC, and followed it up with X-Scale. It's now owned by Marvell, and they're used all over (see Blackberry Torch and the Kindle, for examples...).

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    2. Re:RISC, CISC & VLIW by unixisc · · Score: 1

      Why did they sell it, if it was doing so well? I thought that the reason was there was too much competition in the ARM market to justify Intel remaining in it. It also describes why they spun off their flash division Numonyx.

    3. Re:RISC, CISC & VLIW by godefroi · · Score: 1

      Why did they sell it, if it was doing so well?

      Being neither an officer of Intel nor a shareholder, I haven't any clue why Intel sold it off. My point was that it wasn't exactly a failure as you implied.

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    4. Re:RISC, CISC & VLIW by Anonymous Coward · · Score: 0

      the rumor is that management didn't want to be a third party licensee to ISAs that weren't done in-house. Xscale was sold off to Marvell. i860 and i960 were shut down -- I'm not sure why. itanium still lives, and is apparently making money.

    5. Re:RISC, CISC & VLIW by unixisc · · Score: 1

      Given the pricing of Itaniums, they just have to make money. Have you seen their list price on Intel's own site? But the grand vision Intel & HP once had re: it is gone, as every major ISV except HP has dropped it - Microsoft, Oracle, Red Hat, Canonical, et al the list goes on. In fact, the only OSs that support Itanium now are HP/UX, Debian Linux and FreeBSD. In short, Itanium is no different from Unix only CPUs that existed before, such as the Sparc, PA-RISC and so on. HP Integrity servers are even more niche than HP 9000 servers (based on PA-RISC)

  28. RISC v. CISC is about design approaches by brokeninside · · Score: 1

    Advances in both chip design and software has largely diminished the traditional advantages to RISC design.

    For example, one of the longstanding argument for RISC chips was that because the instruction set was simpler (in terms of the computations, not necessarily in terms of having fewer instructions), it was easier to ramp up clocks speeds. So you had DEC Alphas running rings around x86 chips simply because the DEC kit was running at 500Mhz when Intel was barely able to crack 100Mhz. But advances in chip design have largely leveled the playing field here. Clock speeds are similar between CISC and RISC chips these days.

    Another one of the advantages in RISC design was the ability to keep the pipeline full. But with improvements in branch prediction, out of order operations, and speculative execution, modern CISC designs are almost always able to keep the pipeline full of instructions.

    Not to mention, Intel was able to adapt a good bit of RISC theory in its chips designs. The guts of the modern x86 family are fundamentally different than the days of yore. The x86 instruction set is largely an artificial interface that Intel chips break down into an almost entirely different instruction set internally.

    And then there also the improvements in compiler design. Modern compilers are much better at optimization than they were in 80s and 90s. But this leads to the point you make in your second paragraph. That was effectively the argument for VLIW processors. Yet Itanic didn't seem to pan out so well. It would seem that compilers and programmers just aren't clever enough to make VLIW work well (where working well means better performance than non-VLIW chips doing the same computations). As it turns out, the things that can make a compiler smarter can mostly be applied to compilers for both RISC and CISC chips.

  29. Why RISC was advantageous by unixisc · · Score: 1
    Had most software been written in assembly, and had memory been @ a premium, CISC would indeed have been the better instruction set to follow. In fact, in the early days, when memory was @ a premium, having an architecture where variable length instructions enabled fewer instructions to be required for a program, resulting in smaller programs, which was good for less memory.

    Once C became popular, however, this changed. A few of the reasons were
    • All the instructions in an instruction set weren't necessarily needed or used by a compiler. So all it did was eat silicon & consume real estate
    • Some of the instructions, which used multiple clock cycles, could also be replicated by simpler instructions in the assembly code, which compilers could use
    • On the silicon side, once designers figured out that a CPU could be a lot faster if it didn't need microcode to determine the length of each subsequent instruction, and if that determination itself was eliminated, it made sense to drop the longer instructions, recommending several simpler single cycle instructions instead
    • Once compilers were tuned to support this, RISC processors could run a lot faster @ the same frequency than CISC processors

    This was just the basic underpinnings of the 'RISC is better' school of thought. Over time, RISC itself developed several techniques, and schools of its own. You had super-scalar processors, that increased the number of registers, pipelines and other hardware in the CPU as a result of saving on the microcode - examples of this were the SPARC and POWER CPUs. You also had super-pipelined processors, that diced the various stages of a pipeline even finer, to enable the CPU to run @ higher frequencies - examples being the initial MIPS I & II processors (up to the R4x00 series) and the Alpha 21064s. Over time, superpipelined processors became more superscalar - like the Alpha 21164, while the MIPS switched to superscalar from MIPS III (R5000 onwards), while superscalar processors became more superpipelined in the quest to bump up their frequencies.

    While Intel didn't eliminate microcode itself, it adapted a lot of concepts from the RISC camp, such as multiple registers, pipelines and even superpipelining (Intel called it hyperpipelining). Some companies, like NexGen created RISC processors which had x86 instructions fed in and decoded into internal RISC instructions that got executed. AMD's Athlon - made by the same DEC team that did Alpha after they left DEC for AMD - was their first CPU that didn't have any Intel underpinnings to it, but was a RISC CPU internally, and x86 outside. That was the first time that AMD got an independent CPU design team that weren't just copycats of the x86. And that was the year their fortunes changed.

    To make a long story short, the reason RISC had advantages over CISC was due to the preponderance of higher level languages, whereby if a compiler was simply tuned to use certain instructions in an instruction set, and if that processor ensured that those instructions were the ones supported well in terms of performance, then the apps would fly. This marked a shift in the role of compilers in RISC processing as opposed to CISC processing. This concept worked so well that some companies, and ultimately HP decided to take the argument further, using a concept called VLIW (Very Long Instruction Word). The concept here was to have several independent instructions in a program running in parallel, so that you essentially had a multiprocessor within a CPU, and in addition to the usual things that a RISC compiler did - like register renaming, branch prediction and speculative execution.

    Only problem - unlike the CISC to RISC, RISC to VLIW hit a point of diminishing returns, as I pointed out in my post yesterday below. Much of the real estate that would be saved by a VLIW was minimal, but the complexity of the compilers was really high. VLIW has been used by some companies and has been found to be fine for some applicati

    1. Re:Why RISC was advantageous by Guy+Harris · · Score: 1

      Once C became popular, however, this changed. A few of the reasons were

      • Some of the instructions, which used multiple clock cycles, could also be replicated by simpler instructions in the assembly code, which compilers could use

      And which clueful assembler-language programmers could use as well, especially with a slightly higher-level assembler or lower-level language than C that let you write a single "instruction"/statement that expanded into the instruction sequence in question.

      • On the silicon side, once designers figured out that a CPU could be a lot faster if it didn't need microcode to determine the length of each subsequent instruction,

      You don't need microcode to determine the lengths of instructions - the implemented-entirely-in-hardware System/360 Model 75 didn't, for example.

      This was just the basic underpinnings of the 'RISC is better' school of thought. Over time, RISC itself developed several techniques, and schools of its own. You had super-scalar processors, that increased the number of registers,

      I'm assuming you're talking about register renaming here; superscalar processors don't in and of themselves increase the number of registers. pipelines and other hardware in the CPU as a result of saving on the microcode - examples of this were the SPARC and POWER CPUs. You also had super-pipelined processors, that diced the various stages of a pipeline even finer, to enable the CPU to run @ higher frequencies - examples being the initial MIPS I & II processors (up to the R4x00 series) and the Alpha 21064s. Over time, superpipelined processors became more superscalar - like the Alpha 21164, while the MIPS switched to superscalar from MIPS III (R5000 onwards), while superscalar processors became more superpipelined in the quest to bump up their frequencies.

      While Intel didn't eliminate microcode itself, it adapted a lot of concepts from the RISC camp, such as multiple registers,

      OK, so you almost certainly mean "register renaming"; they went up to 8 registers in the 80386, and AMD (not Intel) went up to 16 registers in x86-64 (Intel followed them there).

      pipelines

      Well, yes, the 80486 was pipelined, but so was the CISC System/360 Model 91 (admittedly, a rather high-end S/360).

      Some companies, like NexGen created RISC processors which had x86 instructions fed in and decoded into internal RISC instructions that got executed. AMD's Athlon - made by the same DEC team that did Alpha after they left DEC for AMD - was their first CPU that didn't have any Intel underpinnings to it, but was a RISC CPU internally, and x86 outside. That was the first time that AMD got an independent CPU design team that weren't just copycats of the x86.

      ...which they got from, err, umm, NexGen.

      The concept here was to have several independent instructions in a program running in parallel, so that you essentially had a multiprocessor within a CPU,

      That's also what you have in a superscalar processor, such as many RISC processors and x86 processors starting with the original Pentium (and, arguably, the somewhat RISCy CDC 6600 and definitely CISC System/360 Model 91).

      and in addition to the usual things that a RISC compiler did - like register renaming, branch prediction and speculative execution.

      Presumably you mean "RISC processor" rather than "RISC compiler" (and branch prediction, at least, didn't originate on RISC processors).

    2. Re:Why RISC was advantageous by unixisc · · Score: 1

      I did imply register renaming when talking about increasing the #registers in a RISC CPU. The same didn't necessarily translate into gains in the x86, even though they increased the register count in the 386, since a lot of the code that the 386 was running was legacy 286 code, which included much more assembly than code written later, particularly for NT or Unix.

      I know that superscalar processors don't by themselves increase the number of registers. And you're right - the extra pipelines that they use were implemented in CISC as well. But on AMD, NexGen's acquisition didn't turn their fortunes, since NexGen had a limited Integer only CPU, which didn't do AMD much good. What the Athlon team put together was an Alpha like CPU.

      On my last statement, I'm sorry I didn't make myself clear. What I meant was that in addition to the functions that a RISC compiler does, a VLIW compiler would also have taken on functions like register renaming, branch prediction and speculative execution, something that was done in silicon on a RISC but in a compiler in VLIW.

  30. Four years late by fragMasterFlash · · Score: 1

    These power and performance numbers finally match what Intel promised to deliver with Atom in 2008, and it took ARM and AMD kicking Atom squaw in the competitive nuts to get them to deliver. This does not bode well for Chipzilla.