TSMC To Spend $10B Building Factory for 450mm Wafers
An anonymous reader writes "With demand for processors growing and costs rising, using larger wafers for manufacturing is highly desirable, but a very expensive transition to make. TSMC just announced it has received approval from the Taiwan government to build a new factory for 450mm wafers, with the total cost of the project expected to be between $8-10 billion. The move to larger wafers isn't without its risks, though. Building new facilities to handle production is the easy part. The industry as a whole has to overcome some major technical hurdles before 450mm becomes a viable replacement for the tried and tested 300mm process. TSMC's chairman Morris Chang has stated the next five years will be filled with technical challenges, suggesting 450mm wafers may not be viable until at least 2017."
How about they focus on fixing their 28nm production problems before they set their eyes on lowering cost through bigger wafers. It's not like many of their most lucrative clients aren't hobbled at the moment by lack of supply for their top bin parts. Oh, yes they are.
There are 4 boxes to use in the defense of liberty: soap, ballot, jury, ammo. Use in that order. Starting now.
Taiwan. Semiconductor. Manufacturing. Company.
Our CEO (based in Silicon Valley) makes regular trips to Taiwan. He tells me of massive developments out there, office parks the size of the city of Fremont are springing up left right and centre. Says there's this government organisation (can't recall its name) that takes in graduates as resident interns, carries out pure research, incubates new companies, and is a driving force behind the country's growth.
Anyone on here from Tawian that can confirm this? Sounds to me like they're kicking ass over there.
Drill baby drill - on Mars
going to a new technology for an industry has risks? [YOU DON'T SAY]
The Kruger Dunning explains most post on
We're doing 500mm!
Fuck systemd. Fuck Redhat. Fuck Soylent, too. Wait, scratch the last one.
...or 14.6ypc
Upward mobility is a slippery slope - the higher you climb the more you show your ass.
I'm sorry, but you're the one making a fool of yourself. The process is 28 nanometers, the wafers are now 300 millimeters wide and will be 450.
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TSMC Chairman Morris Chang told reporters he expected other rivals such as Samsung were also working on developing a 450mm, or 18 inch, wafer.
"18-inch is something we have to do, but the technology is not ready yet ... if we can overcome it, it'll be a big breakthrough," he said after the company's annual general meeting.
I know Europers are bad at reading comprehension, but this isn't the precision of the wafer, it's the size. They're planning to make a lot more chips each run.
450mm refers to wafer size (http://en.wikipedia.org/wiki/Wafer_(electronics)).
28nm refers to a fabrication process (http://en.wikipedia.org/wiki/Semiconductor_device_fabrication).
They're not off by 6 orders of magnitude, you are.
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Yes, and I RECANT.
Upward mobility is a slippery slope - the higher you climb the more you show your ass.
Are you suggesting to build this thing in Australia so that in case of flooding the water will drop into space?
That doesn't explain the fondness for Ramen Noodles.
Don't know something? Look it up. Still don't know? Then ask.
I would be more worried about attacks from the mainland.
"To those who are overly cautious, everything is impossible. "
I can understand if TSMC, or anyone else, were moving from 8" to 12" wafers.
This is going to 18" wafers. (~17.7 inch - close enough that I'd assume it'd be called "18 inch")
300mm wafer are sometimes called 12" wafers. And is what many/most use now.
If someone were moving from 8" to 12" (200mm to 300mm) it's not news at this point - they're years behind others in moving.
Wafer handling is a big deal, and the bigger the wafer the less waste there is at the circumference, increasing yield.
from the those-are-some-small-cookies dept
A ~18" cookie is small to you? Did /. outsource to Brobdingnag ?
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Remember when your mammy told you to proofread before hitting the "Submit" button? Should have listened then, now you look like an idiot for mis-reading the 450mm wafer size for 450nm (presumably the minimal process feature), then trying to be a smart-ass about the perceived incompetence of one of the the largest silicon manufacturers in the whole world.
can someone explain to me why every generation, like changing from 45nm to 32nm lithography or changing wafer size from 300mm to 450mm or whatever takes building a brand new multi-billion dollar fab when you'd think they'd build the machinery and everything that goes along with it to um, 'scale' to some extent? Certainly there must be machines in these fabs that can be re-programmed to handle changing requirements.
You could have a 1m wafer and produce 22nm CPU dies on it.
Hell, I wouldn't be surprised if we see 1m wafers within our lifetime.
Uh, no! They are correctly referring to 450mm *wafers*. 450 mm or about 17.7 inch diameter *wafers*. Not line width wafer diameter. This represents a roughly 125% increase in area over current 300mm wafers, and since the marginal cost of processing a 450mm wafer over a 300mm wafer is no where near 125% (it's mostly in the cost of the newer machinery) TSMC will be able to significantly decrease the cost of their products and so will companies like NVidia, ATI, Broadcom and Qualcomm (NOT Apple they don't make chips at TSMC yet). We Americans may not be great at using the SI system but at least we know what where talking about.
It is big, but then so is the US and more cutting edge research is going on here. Intel is already on the 22nm node, and I don't mean playing with, I mean shipping chips in mass quantities to retailers and OEMs (Ivy Bridge). TSMC is on the 28nm half node currently, with plans to go to the 20nm half node about the time Intel goes to the 14nm half node.
In terms of 450mm wafers, well Intel is going there too or at least that is the plan. Fab 42 is under construction in Chandler Arizona right now and will be 14nm process, 450mm wafer. It is slated to start commercial production in 2013, and Intel has been pretty damn good about hitting its dates on fabs.
No doubt Taiwan is big for semiconductor fabrication, as TSMC is one of the biggest fab-for-hire outfits out there. However if you think all the R&D is going on there, all it means is you've not paid attention to Intel. They are ahead of all other processes currently (and usually are) and they upgrade at a fantastic rate. They do real ground breaking research too, and have to as they are usually leading the pack. One cool thing they have in their latest process is multi-gate transistors, which is a first for CPUs as far as I know.
. . .is that it's cut from a single silicon crystal (called a boule), two meters long, weighing several hundred kilos, with a defect density so low that it is commercially useable to make chips 25 mm on a side, 0.5 mm thick, with 20 nm feature size.
"Intel Corp., Samsung Electronics and TSMC today announced they have reached agreement on the need for industry-wide collaboration to target a transition to larger, 450mm-sized wafers starting in 2012." -- 6 May 2008.
Thank you
Drill baby drill - on Mars
My estimates put the Die's per Wafer at:
300mm = 58615762400 DPW
450mm = 10228963043666936 DPW
If the newest 22nm process is used. By the time the factory gets up and running there may be even better efficiencies that could be adapted. It is an expensive venture but at some point either the economics work out or you need to build a new factory anyways. It is good to see progress.
There is or can be built a machine that can simulate any physical object. -Church-Turing principle
I would love to see a 450 mm die. More than that, I'd love to see the probe card used to test it.
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I know USAns are terrible at metric system, but skewing the prefix by 6 orders of magnitude is just plain stupid. To make it easier for you USAns it's 450nm or 177nin (nanoinches, not Nine Inch Nails).
Incorrect. It is 450 millimeters (mm) in diameter. This translates to an approximately 18 inch diameter wafer. And that is huge. It needs completely new tools and materials handlers to be designed and tested; you can't just upsize the existing things, especially given the drive to decrease the thickness of wafers, thus increasing their fragility.
TSMC will be able to significantly decrease the cost of their products and so will companies like NVidia, ATI, Broadcom and Qualcomm (NOT Apple they don't make chips at TSMC yet)
COST vs PRICE.
We Americans
Are you talking on behalf of both continents?
we know what where talking about
WMDs in Iraq (BTW you can't even pronounce Iraq properly), Iran building nuclear weapons, cannabis being a "dangerous drug" on par with heroin, um... [job] creationism. No. If your "elite," creme de la creme looks that stupid, what can be said about the average? "Is your children learning?"
Upward mobility is a slippery slope - the higher you climb the more you show your ass.
Take a wild guess.
Upward mobility is a slippery slope - the higher you climb the more you show your ass.
Europers
It's Europeans, and how can you be sure you even hit the right CONTINENT?
Upward mobility is a slippery slope - the higher you climb the more you show your ass.
Oh, thanks, I did misread it as 450nm rather than 450mm. I'm more used to hearing about 6", 8", 12" wafers, so I'd have thought that using 16" would have been more like it. Thanks, 'mammy'! Now the article makes a lot more sense.
I doubt that they'll grow anywhere near that, b'cos beyond a point, the risk of breakage of the wafers as they get transported from fabs to assembly is much higher. Maybe they'll increase the #wafers that constitute a lot?
Why use millimeters to define the wafer sizes when they are growing, not shrinking? Initially, we used to use microns to define lithographies, but when we got to 0.25 microns, we started using nm. In the case of wafer sizes, since we went from 6" to 8" to 12" to now 16", why not use cm to describe their sizes - 15cm, 23cm, 30cm and 45 cm? And thanks for not making fun of my reading comprehension - the units do look similar, and in the late 90s, I was working w/ a company who was at that time in the 0.45 micron process, which would be 450nm. So it didn't look that far fetched, which is why I was surprised.
Thanks to you and everyone else in this thread for clearing it - somehow, I didn't notice it was 450mm. Incidentally, is TSMC the first company to move to 18" wafers? Or have Intel and other leading fabs moved there already?
When will they learn!? Size doesn't matter! It's all about the frequency!
The more it hertz the better!