MIPS Technologies Porting Android 4.1 to MIPS Architecture

angry tapir writes with news on Android getting support for a third architecture. From the article: "ARM rival MIPS is continuing its push to make a mark in low-cost tablets and quickly trying to bring Android 4.1 (Jellybean) to its processors. 'We are working aggressively on bringing Jelly Bean to MIPS, and expect that it will be available to our licensees very soon,' said Jen Bernier-Santarini, director of corporation communications at MIPS, in an email. Tablets with MIPS processors are largely low-cost and have found buyers mostly in developing countries. MIPS last week said a new tablet called Miumiu W1 from Chinese company Ramos would become available in a few months in India, Latin America and Europe. The tablet has a 7-inch screen, a MIPS processor running at 1GHz, front camera and a microSD slot for expandable storage."

Comments

In case you're wondering

[slashmydots]

Good, finally ARM manufacturers will stop having a monopoly where they can charge whatever they want. I've seen hints at OEM chip prices and they're ridiculous compared to even desktop chips. That will help everyone...just in time for x86 tablets to come out so people can actually run whatever they want.

By the way, if you're wondering as I did but were too lazy to look it up, yes, they actually named themselves MIPS without noticing that that's also Millions of Instructions Per Second, a method for measuring the speed of any CPU. Theirs stands for Microprocessor without Interlocked Pipeline Stages and it refers to an instruction set. What an unfortunate oversight. Stages could have been replaced with just about any other word to differentiate it.

Re:In case you're wondering

[bluefoxlucid]

OEM chip prices like the Tegra 3 at $35 for a quad core 1.4GHz with a fifth extremely-low-power core bounded to 500MHz in single processor mode? With a full system-on-chip including system bridges, memory controllers, and full nVidia graphics, $35 is ridiculous. Why a quad core Sandy Bridge processor doesn't cost half that!

Re:In case you're wondering

[fuzzyfuzzyfungus]

To what degree are 'ARM manufacturers' reasonably a monopoly? The rise of ARM devices whose performance people give a fuck about does seem to have opened room for whoever is currently selling the hottest part on the street to charge a nontrivial premium; but cut back a bit from the bleeding edge and it's a veritable knife-fight of utterly undistinguished and cheap offerings.

Fragmentation

[Dan East]

Great. Now we'll see the same fragmentation Windows CE had all those years. Most games use the NDK and contain binary compiled specifically for ARM. Obviously those apps will not run on the MIPS processor. Microsoft eventually learned this was not a good thing and finally forced all OEMs to use ARM to qualify for Pocket PC branding.

Now all we need is Android running on SH3 and we'll have gone full circle.

Re:Fragmentation

[Tapewolf]

Great. Now we'll see the same fragmentation Windows CE had all those years. Most games use the NDK and contain binary compiled specifically for ARM. Obviously those apps will not run on the MIPS processor.

The NDK now has MIPS support out of the box. Going forward it would probably be a good idea to compile for all supported targets.

Re:Fragmentation

[bluefoxlucid]

It doesn't matter really. ARM uses some 0.1-1.0W, MIPS uses 10-20W for slower clock speeds. ARM has fixed-width single-decode instructions; MIPS has three types of instructions of variable width. ARM does damn near everything in one clock, including evaluate-and-execute prefixed instructions ( { if ( n ) m = 5; } is 2 insns: 'cmp n' and a prefixed 'movnz m, 5'. If n == 0, movnz means 'nop'; otherwise it means 'mov'. Instead of 'cmp n; jnz @@a; mov m,5; @@a:' where jnz and mov have to be evaluated in separate stages. Yes it's been 11 years since I did assembly, it was 286 and 6502, and I'm unfamiliar with ARM by far). MIPS is slow. You may as well put an Intel CELERON in there if you go MIPS.

Re:Fragmentation

[YoopDaDum]

ARM uses some 0.1-1.0W, MIPS uses 10-20W for slower clock speeds.

Not anymore, by far. Forget about MIPS as in Silicon Graphics workstations ages ago. Now MIPS is an embedded IP provider, very similar to ARM. And they do have low power cores quite similar to ARM. Who is on top in mW/MHz changes over time, but MIPS do have some competitive offers.

Now what ARM has for it is that it became the defacto architecture for mobile (nobody got fired to chose ARM and all that), and it has much more resources than MIPS. So ARM has a more extensive IP offer, and can work on process optimization too. By this I mean that where MIPS will provide a soft core in RTL, ARM can also provide hard macros optimized for some fab process. And even if you want to go soft core and optimize yourself, ARM can provide a ready to use optimization package to get you started.

ARM has fixed-width single-decode instructions; MIPS has three types of instructions of variable width.

No, they're actually very similar: their native instruction size is 32 bits, but both support a 16 bits instruction mode which is in its second generation in each case (Thumb2 for ARM, can't remember the MIPS name... Maybe MIPSe?).

MIPS is slow. You may as well put an Intel CELERON in there if you go MIPS.

Why the comparison with a discrete chip? MIPS do no sell discrete chips anymore, it's all IP. Then in IP they have offer that are performance competitive with the same class ARM. I'd give the edge in the high end to ARM though, thanks to their close work with the fab to optimize their implementation.

Re:Fragmentation

[TheRaven64]

Also, if conditional prefixes were so great, why's ARM64 eliminating them.

ARMv8 is not eliminating them, it's reducing the number of instructions that have them. Conditional instructions are useful because you can eliminate branches and so keep the pipeline full. For example, consider this contrived example:

if (a < b)
a++;

On ARMv7 and earlier, this would be a conditional add. The pipeline would always be full, the add would always be executed, but the result would only be retired if the condition is true. On MIPS, it would be a branch (complete with the insanity known as branch delay slots, which if you look at the diassembly of most MIPS code typically means with a nop, so you get to waste some i-cache as well) and if it's mispredicted then you get a pipeline stall.

On ARMv8, you don't have a conditional add, but you do have a conditional register-register move and you have twice as many registers. The compiler would still issue the add instruction and then would do a conditional move to put it in the result register. From the compiler perspective, this means that you can lower PHI nodes from your SSA representation directly to conditional moves in a lot of cases.

Basically, 32-bit ARM is designed for assembly writers, ARMv8 is designed for compilers. As a compiler writer, it's hands-down the best ISA I've worked with, although I would prefer to write assembly by hand for ARMv7. I wouldn't want to do either with MIPS, although I currently am working on MIPS-based CPU with some extra extensions.

Incidentally...

[fuzzyfuzzyfungus]

Forgive my ignorance; but when and how did MIPS get relegated to second-class status? I still see them crop up from time to time, certain cheapy router SoCs still come out with MIPS cores; but ARM appears to have gone rampaging across much of the territory that Intel hasn't already entrenched themselves in.

Was there a fuckup or an epic design win at some point in the past?