MIPS Technologies Porting Android 4.1 to MIPS Architecture

angry tapir writes with news on Android getting support for a third architecture. From the article: "ARM rival MIPS is continuing its push to make a mark in low-cost tablets and quickly trying to bring Android 4.1 (Jellybean) to its processors. 'We are working aggressively on bringing Jelly Bean to MIPS, and expect that it will be available to our licensees very soon,' said Jen Bernier-Santarini, director of corporation communications at MIPS, in an email. Tablets with MIPS processors are largely low-cost and have found buyers mostly in developing countries. MIPS last week said a new tablet called Miumiu W1 from Chinese company Ramos would become available in a few months in India, Latin America and Europe. The tablet has a 7-inch screen, a MIPS processor running at 1GHz, front camera and a microSD slot for expandable storage."

Comments

In case you're wondering

[slashmydots]

Good, finally ARM manufacturers will stop having a monopoly where they can charge whatever they want. I've seen hints at OEM chip prices and they're ridiculous compared to even desktop chips. That will help everyone...just in time for x86 tablets to come out so people can actually run whatever they want.

By the way, if you're wondering as I did but were too lazy to look it up, yes, they actually named themselves MIPS without noticing that that's also Millions of Instructions Per Second, a method for measuring the speed of any CPU. Theirs stands for Microprocessor without Interlocked Pipeline Stages and it refers to an instruction set. What an unfortunate oversight. Stages could have been replaced with just about any other word to differentiate it.

Re:In case you're wondering

[bluefoxlucid]

OEM chip prices like the Tegra 3 at $35 for a quad core 1.4GHz with a fifth extremely-low-power core bounded to 500MHz in single processor mode? With a full system-on-chip including system bridges, memory controllers, and full nVidia graphics, $35 is ridiculous. Why a quad core Sandy Bridge processor doesn't cost half that!

Re:In case you're wondering

[ericloewe]

They've been around for ages... Anyone who might need/want to know the architecture can easily differentiate MIPS from MIps, just ike everybody can distinguish ARM from arm.

Re:In case you're wondering

[tepples]

OEM chip prices like the Tegra 3 at $35

As a comment to a recent anti-Ouya story on Slashdot pointed out, even the data sheet for the Tegra 3 is available only to the highest volume manufacturers.

Re:In case you're wondering

[slashmydots]

As long as it's in all caps, nobody should misunderstand it...unless they say "IT'S AN ARM-KILLING TABLET!" which definitely implies it's extremely heavy, lol.

Re:In case you're wondering

[daid303]

Good, finally ARM manufacturers will stop having a monopoly where they can charge whatever they want.

I though ARM processors were really inexpensive, we keep seeing cheaper and cheaper tablets, computers like the RaspberryPi, MK802, etc, all based on ARM
ARM have a monopoly, yeah, but it's because they're really better on price, performance and power consumption (AFAIK)

They are. But people always want cheaper and see monopolies where they want. To compare, we are currently in the process of replacing a 50 euro PowerPC chip with an 7 euro ARM chip, which is faster and more capable.

Re:In case you're wondering

[fuzzyfuzzyfungus]

To what degree are 'ARM manufacturers' reasonably a monopoly? The rise of ARM devices whose performance people give a fuck about does seem to have opened room for whoever is currently selling the hottest part on the street to charge a nontrivial premium; but cut back a bit from the bleeding edge and it's a veritable knife-fight of utterly undistinguished and cheap offerings.

Re:In case you're wondering

[bluefoxlucid]

It's probably actually higher grade. The massive power output of a 50-200W processor is due to leakage--that is, it's due to poor efficiency. The Intel Atom for example was designed to leak less, and Intel's tighter packaging and lower TPD CPUs are based on new fabrication process that allows greater electrical efficiency. Bloated, poorly thought out designs bleed power as standing static field and heat--standing static field prevents smaller process, i.e. an imprecisely made junction will work on a 90nm process but at 32nm will bleed signal into all adjacent junctions and cause errors. Improving fidelity reduces bleed, allowing for a smaller process.

Somebody will clean up the stuff I glossed over for lack of understanding. The above's all just basics.

Re:In case you're wondering

[Anonymous Coward]

MIPS has been around for some time. They used to make RISC processors for workstation class machines and even had a Windows NT distribution that was geared to high performance floating-point operations. This was in the early nineties when there were competitors in the 32-bit windows platform. DEC-Alpha, Intel, MIPS all had versions of Windows NT, and there were versions of AutoCAD, 3D Studio, and some of the Adobe products as well.

MIPS biggest success at the time was their use in SGI workstations that fueled the early nineties CGI craze. MIPS also produced the processor at the heart of the N64.

RISC architecture didn't win the desktop/workstation battle so companies like MIPS and ARM moved on to efficient platforms that end up powering low-power/portable devices like tablets/phones.

Re:In case you're wondering

[Narishma]

MIPS also produced the processor at the heart of the N64.

And the PS2 and PSP and multitudes of routers and set top boxes.

Re:In case you're wondering

[unixisc]

Fully agree w/ all of the above posters. If any CPU has covered the entire spectrum of low power to high performance, it's been MIPS. Alpha used to be known for its excessively high power dissipation, PPC's low power offerings rarely was low in power consumption, ARM rarely had the performance, while PA-RISC and SPARC hardly played in the low power space. It's tragic that MIPS has lost the console market to the PPC, but they can still recoup w/ both tablets and low power servers. Currently, AFAIK, it's still the most popular for networking gear.

One unusual change that MIPS did was to go from a super-pipelined architecture to super-scalar when they introduced MIPS-IV. Alpha, by contrast, went from just super-pipelined to super-scalar, super-pipelined, while Intel went from super-scalar to super-scalar, super-pipelined. Nobody else went for super-pipelining, since the frequency increases wouldn't result in a substantial performance increase.

Incidentally, anyone know who the current manufacturers of MIPS are, outside China's Loongson and XBurst? Do NEC, QED or anyone else still make them? Also, which ones are popular - the ones based on the R4x00 or the ones based on the R50000 (MIPS IV)?

Aside from the MIPS, there is also OpenRISC, which uses most of the MIPS instructions, but w/ some exceptions. Wonder whether anybody would fab them, and how they would compare against the MIPS?

Re:In case you're wondering

[TheRaven64]

One disadvantage MIPS has is that it has a completely batshit insane architecture full of things that kind-of vaguely made sense in a research project and have been a liability for over a decade.

I'm currently working the MIPS back end in LLVM and every day brings a new WTF. ARM, at least, has a mostly sane architecture and in the 64-bit variant has removed a load of stuff that doesn't make sense with newer pipeline designs (e.g. store multiple, conditional adds, and so on). MIPS just accumulates legacy cruft. It's not quite as bad as x86 in that regard, but it's also an astonishingly verbose instruction set. Where ARM or x86 can do something in 2-3 instructions, MIPS is lucky to manage in half a dozen. It's not a coincidence that the decline of MIPS on the high end coincided with instruction cache utilisation being important. Oh, and every MIPS vendor adds some extra incompatible changes to the instruction set just to make life even more fun.

Re:In case you're wondering

[cachimaster]

OEM chip prices like the Tegra 3 at $35 for a quad core 1.4GHz with a fifth extremely-low-power core bounded to 500MHz in single processor mode? With a full system-on-chip including system bridges, memory controllers, and full nVidia graphics, $35 is ridiculous. Why a quad core Sandy Bridge processor doesn't cost half that!

Is that a sarcastic question?
Tegra 3 and ARM in general is low power because it's small. You probably can pack 20 ARM cores inside a Sandy Bridge Core, even the Intel Atom, the smallest x86 core, is big next to an ARM core. You are comparing Apples to Oranges.

Fragmentation

[Dan East]

Great. Now we'll see the same fragmentation Windows CE had all those years. Most games use the NDK and contain binary compiled specifically for ARM. Obviously those apps will not run on the MIPS processor. Microsoft eventually learned this was not a good thing and finally forced all OEMs to use ARM to qualify for Pocket PC branding.

Now all we need is Android running on SH3 and we'll have gone full circle.

Re:Fragmentation

[Tapewolf]

Great. Now we'll see the same fragmentation Windows CE had all those years. Most games use the NDK and contain binary compiled specifically for ARM. Obviously those apps will not run on the MIPS processor.

The NDK now has MIPS support out of the box. Going forward it would probably be a good idea to compile for all supported targets.

Re:Fragmentation

[bluefoxlucid]

It doesn't matter really. ARM uses some 0.1-1.0W, MIPS uses 10-20W for slower clock speeds. ARM has fixed-width single-decode instructions; MIPS has three types of instructions of variable width. ARM does damn near everything in one clock, including evaluate-and-execute prefixed instructions ( { if ( n ) m = 5; } is 2 insns: 'cmp n' and a prefixed 'movnz m, 5'. If n == 0, movnz means 'nop'; otherwise it means 'mov'. Instead of 'cmp n; jnz @@a; mov m,5; @@a:' where jnz and mov have to be evaluated in separate stages. Yes it's been 11 years since I did assembly, it was 286 and 6502, and I'm unfamiliar with ARM by far). MIPS is slow. You may as well put an Intel CELERON in there if you go MIPS.

Re:Fragmentation

[YoopDaDum]

ARM uses some 0.1-1.0W, MIPS uses 10-20W for slower clock speeds.

Not anymore, by far. Forget about MIPS as in Silicon Graphics workstations ages ago. Now MIPS is an embedded IP provider, very similar to ARM. And they do have low power cores quite similar to ARM. Who is on top in mW/MHz changes over time, but MIPS do have some competitive offers.

Now what ARM has for it is that it became the defacto architecture for mobile (nobody got fired to chose ARM and all that), and it has much more resources than MIPS. So ARM has a more extensive IP offer, and can work on process optimization too. By this I mean that where MIPS will provide a soft core in RTL, ARM can also provide hard macros optimized for some fab process. And even if you want to go soft core and optimize yourself, ARM can provide a ready to use optimization package to get you started.

ARM has fixed-width single-decode instructions; MIPS has three types of instructions of variable width.

No, they're actually very similar: their native instruction size is 32 bits, but both support a 16 bits instruction mode which is in its second generation in each case (Thumb2 for ARM, can't remember the MIPS name... Maybe MIPSe?).

MIPS is slow. You may as well put an Intel CELERON in there if you go MIPS.

Why the comparison with a discrete chip? MIPS do no sell discrete chips anymore, it's all IP. Then in IP they have offer that are performance competitive with the same class ARM. I'd give the edge in the high end to ARM though, thanks to their close work with the fab to optimize their implementation.

Re:Fragmentation

[TheRaven64]

Also, if conditional prefixes were so great, why's ARM64 eliminating them.

ARMv8 is not eliminating them, it's reducing the number of instructions that have them. Conditional instructions are useful because you can eliminate branches and so keep the pipeline full. For example, consider this contrived example:

if (a < b)
a++;

On ARMv7 and earlier, this would be a conditional add. The pipeline would always be full, the add would always be executed, but the result would only be retired if the condition is true. On MIPS, it would be a branch (complete with the insanity known as branch delay slots, which if you look at the diassembly of most MIPS code typically means with a nop, so you get to waste some i-cache as well) and if it's mispredicted then you get a pipeline stall.

On ARMv8, you don't have a conditional add, but you do have a conditional register-register move and you have twice as many registers. The compiler would still issue the add instruction and then would do a conditional move to put it in the result register. From the compiler perspective, this means that you can lower PHI nodes from your SSA representation directly to conditional moves in a lot of cases.

Basically, 32-bit ARM is designed for assembly writers, ARMv8 is designed for compilers. As a compiler writer, it's hands-down the best ISA I've worked with, although I would prefer to write assembly by hand for ARMv7. I wouldn't want to do either with MIPS, although I currently am working on MIPS-based CPU with some extra extensions.

Re:Fragmentation

[pchan-]

ARMv8 is not eliminating them, it's reducing the number of instructions that have them. Conditional instructions are useful because you can eliminate branches and so keep the pipeline full. For example, consider this contrived example:

if (a < b)
  a++;

On ARMv7 and earlier, this would be a conditional add. The pipeline would always be full, the add would always be executed, but the result would only be retired if the condition is true. On MIPS, it would be a branch (complete with the insanity known as branch delay slots, which if you look at the diassembly of most MIPS code typically means with a nop, so you get to waste some i-cache as well) and if it's mispredicted then you get a pipeline stall.

On ARMv8, you don't have a conditional add, but you do have a conditional register-register move and you have twice as many registers. The compiler would still issue the add instruction and then would do a conditional move to put it in the result register. From the compiler perspective, this means that you can lower PHI nodes from your SSA representation directly to conditional moves in a lot of cases.

Basically, 32-bit ARM is designed for assembly writers, ARMv8 is designed for compilers. As a compiler writer, it's hands-down the best ISA I've worked with, although I would prefer to write assembly by hand for ARMv7. I wouldn't want to do either with MIPS, although I currently am working on MIPS-based CPU with some extra extensions.

Actually, ARM's reasoning is that modern branch predictors on high end AP's can do a good enough job of following a test and branch and keeping the pipeline(s) full that there is very little value in conditional instructions on future chips. It's hard to cause a pipeline stall or bubble by branching a few instructions forward or back on these CPUs since they are decoding well in advance of the execution pipelines. Added to that, there is an energy cost in executing an instruction and throwing away the result. Obviously, not all cases are wins. In the example you noted, a register to register mov on a register-renaming system is basically a 0-cycle operation (never makes it out of the instruction decoder), so it's hard to do better than that.

Incidentally...

[fuzzyfuzzyfungus]

Forgive my ignorance; but when and how did MIPS get relegated to second-class status? I still see them crop up from time to time, certain cheapy router SoCs still come out with MIPS cores; but ARM appears to have gone rampaging across much of the territory that Intel hasn't already entrenched themselves in.

Was there a fuckup or an epic design win at some point in the past?

Re:Incidentally...

[k(wi)r(kipedia)]

Wikipedia is your friend. Apparently, like an unwanted child, the company got passed around a few times, being bought by SGI, only to be spun out again. It's easy to speculate how an engineer working for an unstable company like that would have other things in mind besides designing the fastest and greatest processors.

Re:Incidentally...

[Anonymous Coward]

MIPS is stuck in an unfortunate limbo between ARM and PowerPC. They lost the home console market to PowerPC (PS1, PS2, N64 were MIPS, but NGC, 360, Wii, PS3 are PowerPC). They lost the portable console market to ARM (PSP was MIPS, PS Vita is ARM, and Nintendo went straight from Z80 to ARM). They're still popular for el cheapo home routers, but they're being squeezed by ARM on one side (small servers/plug-boxes/routers) and by PowerPC and Atom on the other side (NAS, larger home servers). Pro networking gear, of course, runs on PowerPC.

This is a doomed attempt to gain a small slice of the cheapo Chinese tablet market, but honestly, with Chinese ARM chips like the Allwinner A10 out there, their chances of success are minimal.

Re:Incidentally...

[YoopDaDum]

I'm not sure that MIPS is so well placed in the high-end. Yes, they've been high end a long time ago and have had 64 bits support for ages. But today it's a different game, they provide embedded IP now. And where ARM can help their customers optimizing the implementation for a given process (ARM gains this experience by making hard macros and working closely with TSMC, GlobalFoundries...), MIPS has much less resource and just do soft macros. Then up to you to do the optimization. In other words, if you go ARM for an embedded high-performance SoC IP you can leverage a lot of work that ARM does, that you will have to do with MIPS. To get an implementation that is less common in the end.

So the high end may be tough for MIPS. But in the medium end, where price is critical and performance less so, they can be an interesting choice.

MIPS - there's a blast from the past

[Chrisq]

I remember when Windows ran on MIPS!

Re:MIPS - there's a blast from the past

[obirt]

http://www.netbsd.org/ports/pmax/ :)