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Mass Production of 450mm Wafers Bumped Back Again: 2018
Taco Cowboy writes with news on the slipping schedules in the move toward both larger wafers and 3D integrated circuits in the semiconductor fab world. From the articles: "TSMC ... said it planned to start mass-producing next-generation 450mm wafers using advanced 10-nanometer technology in 2018. The advanced 10-nanometer chips could first be used in mobile devices and other consumer electronics, like game consoles, that demand high-performance and low power consumption. The plan was included in the latest technology roadmap unveiled by TSMC about one year after the chipmaker attributed its delay in making 450mm wafers, originally scheduled in 2015, to semiconductor equipment suppliers' postponement in developing advanced equipment for manufacturing amid the industrial slump. Chipmakers can get 2.5 times more chips from a 450mm wafer than from a 300mm wafer ... The industry's gradual migration toward 3D ICs with through-silicon vias (TSV) is unlikely to happen until 2015 or 2016, according to sources at semiconductor companies. Volume production of 3D ICs was previously estimated to take place in 2014. Leading foundries and backend assembly and test service companies have all devoted much of their R&D efforts to TSV development, and are making progress. The major players are believed to be capable of supporting 3D ICs by 2014, but the emerging technology going into commercial production may not take place until around the 2015-16 timeframe."
Probably one of the most interesting presentations at HOPE9, "Indistinguishable From Magic: Manufacturing Modern Computer Chips," covered modern semiconductor fabrication and why these things are cool. If you're interested in more background (what do all of those TLAs mean?), check out the slides / audio (or attached video of the presentation from YouTube).
As we all know, however much They don't want us to, the pace of 'innovation' in semiconductor fabrication is based almost entirely on the reverse engineering of artefacts taken from crashed Grey spacecraft.
Unfortunately, a recent downturn in the tourism sector of Theta Epsilon Minus, caused by the booming popularity of direct neural hedonostimulator technology, has sharply reduced our supply of samples...
Don't care about the latest technology, they will never improve on the technology in Nilla Wafers http://www.nabiscoworld.com/Brands/brandlist.aspx?SiteId=1&CatalogType=1&BrandKey=nilla&BrandLink=/nilla/&BrandId=76&PageNo=1
That's almost half a meter. That's gong to be one big CPU.
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I like Peanut Butter on my Nilla Wafers
But
Prefer Nacho Cheese dip for my Silicon Chips
We are Dead Stars looking back Up at the Sky
Called D1X (development, but also production like previous "X" fabs) in Oregon, with a second to follow. 450mm wafer production will likely hit volume levels by 2014, just not at the foundries listed in the story.
Price conscious, volume manufacturers like semi foundries would be more willing to push back adoption dates if the investment isn't likely to pay for itself. Most of their business is usually on n-1 or n-2 process nodes. This changeover just happens to be particularly expensive and may not yet make economic sense for another 2-3 years.
There are few products that need that kind of production. For everyone else it is just too damn expensive.
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That's because Intel is years ahead of the other foundries and has been for some time. The spend countless billions a year on their fab processes.
In a steaming pile of lies.
Eventually they will run into a technical problem that they can't solve. Marketers will continue to say 'it's all good, we're just pushing it back another year'.
I'm not saying this is the end. But it will eventually hit a wall.
John McAfee 'It was like that time I hired that Bangkok prostitute; to do my taxes, while I fucked my accountant'
Oh god, how did they fix the problems? Isn't that the sizes where tunneling, leakage and even casimir become really major?
You should take this Intel announcement with a big handful of salt. Intel doesn't make the waver producing machinery, they get it from companies like ASML.
Now, there's been a big struggle between companies like Intel that wanted 450mm earlier, and the tool makers who sank a lot of money on the move to 300mm before and don't want to be burned again in the move to 450mm. The Intel announcement above was to put pressure on the tools providers. It didn't worked out in the end.
All this got sorted out between big boys recently, with Intel, TSMC and Samsung investing a lot of money in ASML to speed-up the availability of 450mm. But the accelerated roadmap has nothing to do with the announcement you quote, just look at it from ASML direct (slide 14). The 450mm process development tools are worked on starting mid-2015 and production equipment is available beginning of 2018. Exactly what is said in the TFA.
450mm is important as it is the only known step that will bring the cost of chips down. Other planned changes (finer processes, 3D chips...) increase performance but also cost. But 450mm requires huge upfront investments, so you need large volumes to recoup it and it will require a big upfront spending. Which is why a lot of people are pushing back. Intel has both high volumes, high margins and deep pockets so they're the most eager to get started. But as you can see, even with their backing it's not that simple and fast.
current wafers still yield large numbers of current-sized chips. and for the most part, chip architects are not primarily limited by available area: relentless process shrinks bring, if anything, more transistors than they know how to use. sure, you can always throw on more cache, especially L3. but the main issues today are power and IPC/TLP-type efficiency, not space. the K20 team at NVidia might disagree, but they _should_ be pushing the bounds, since their target is less cost-sensitive HPC, not commodity/gaming.
in short, the action is in litho, process, transistor topology, power and microarchitecture, not the number of chips spoiled by the edges.
So do other manufacturers.
I don't think TSMC spends as much as Intel on R&D.
If the move to bigger wafers is driven strictly by increased efficiency there's no incentive to rush to adopt it. It's no different than rushing out to buy a marginally more fuel efficient car. It's going to take years to make up the difference in savings, if that ever even happens.
The move to 450mm wafers is a massive investment. Twelve years ago I had the opportunity to visit a new 300mm foundry for TSMC's big Taiwanese competitor UMC. The entire line was built around that size; everything from the cases that hold the wafers, to the tracks that transport them to the units that do the lithography. So you can't just swap out a production line. They'd almost certainly just build a new facility, which is not trivial in it's own right. But again, not much reason to bother if all it will enable you to do is get more units on one wafer.
And that isn't even accounting for the technical difficulties in simply making larger wafers. A lot of problems have already been addressed at the current sizes, but the bigger sizes introduces a host of new challenges. And when it comes down to it, there's 10-nanometer chips don't inherently require a bigger wafer.
Given the fact that foundries have ramped down production because of decreased demand there's even less incentive to go bigger.
No. D1X is just 450mm ready. There are no 450mm production tools available and the top equipment suppliers are only now working on prototype 450mm tools. It takes a minimum of 2 years for Intel to ramp a process and they need a full fab of production 450mm tools to do so. But before then they need a pilot line to play around with. Since they do not have any of this now in late 2012 there is no way they will have anything ramping in 450mm by 2014.
I know this because I work in the equipment industry and 450mm is still top secret and not mentioned at all in press releases. 450 pilot lines are setup at IMEC and the Albany CNSE but many of the tools are from smaller vendors that don't really have a chance in hell of making it into Intel's production line.
Intel's R&D budget alone is around 70% of TSMC's total yearly revenue for example. Also, if you look up rankings of R&D spending by technology companies Intel's is basically the second highest just behind Microsoft.
Without the software guys, quite a few of you hardware guys would be out of a job too. Demand for hardware would be pretty low if we went back to entering commands through switch panels again.
The lithography is one aspect but what about the deposition/etching equipment? It is spread across multiple vendors and getting them all to support 450mm is going to be one heck of a challenge when for the most part they have only just gotten 300mm production perfected. The chip manufacturers won't/can't settle for 450mm tools that don't hit or exceed the quality of work produced by current 300mm tools because the process nodes now depend on that quality to produce working chips. Maintaining anisotropic plasma etch selectivity or deposition thickness uniformity on over double the area without resorting to much slower processing is going to be a really tough target to hit.
That's because Intel is years ahead of the other foundries and has been for some time. The spend countless billions a year on their fab processes.
Per Intel's January 2012 earnings report, their plan for this year is:
Capital spending: $12.5 billion, plus or minus $400 million
R&D spending: approximately $10.1 billion.
Which, compared to the size of my bank account, is "countless" :)
I'm without mod points today, but you bring up an extremely important issue. Uniformity of processes across the surface of a 450mm wafer will be very difficult to achieve. I thought it was a pain in the ass to adjust some epitaxial processes for 200mm wafers when I was still working in the semi industry. I can't imagine the hassle of going to 300mm let alone 450mm. Litho is much easier as it's really just an optical process. Ensuring uniform reactor temperature, or solution chemistry across half a meter is a lot harder.
No. D1X is just 450mm ready.
Similarly, I think the GlobalFoundries fab in Malta, NY is supposedly "450mm ready" or maybe the annex will be. But regardless, "450mm ready" doesn't mean all that much.
Who do you get to be an expert to tell you something's not obvious? The least insightful person you can find? -J Roberts
Exactly, once the wafer is chucked and aligned litho is really only concerned with little 40mm by 80mm blocks of the wafer and the rest is just step and repeat. Several years ago when I left the industry the 300mm litho tools were already fully capable of introducing exposure-by-exposure correction offsets, with different correction maps depending on what exposure system the wafer ran on for a previous exposure layer. However everything is always focused on the exposure side because they are the most expensive equipment in terms of wafers produced per hour per $ of cost due to all those fancy Zeiss optics.
I remember some plasma etch and CVD engineers singing the praises of 300mm, but I think that was mostly because the wafer flats were replaced by notches and better automation keep their equipment consistently loaded. The Chemical Mechanical Planarization engineers however were never having a good time and that is going to be a beast and a half for 450mm.
He's just trolling. If he knew anything about hardware engineering he would know that current hardware would be impossible to design without the aid of software tools.
R&D spending: Hrair dollars.
you countless comment reminded me I guess
It would be very interesting to have Intel running a 450mm wafer FAB when there is no one supplying the FAB machines !!
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