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Mass Production of 450mm Wafers Bumped Back Again: 2018
Taco Cowboy writes with news on the slipping schedules in the move toward both larger wafers and 3D integrated circuits in the semiconductor fab world. From the articles: "TSMC ... said it planned to start mass-producing next-generation 450mm wafers using advanced 10-nanometer technology in 2018. The advanced 10-nanometer chips could first be used in mobile devices and other consumer electronics, like game consoles, that demand high-performance and low power consumption. The plan was included in the latest technology roadmap unveiled by TSMC about one year after the chipmaker attributed its delay in making 450mm wafers, originally scheduled in 2015, to semiconductor equipment suppliers' postponement in developing advanced equipment for manufacturing amid the industrial slump. Chipmakers can get 2.5 times more chips from a 450mm wafer than from a 300mm wafer ... The industry's gradual migration toward 3D ICs with through-silicon vias (TSV) is unlikely to happen until 2015 or 2016, according to sources at semiconductor companies. Volume production of 3D ICs was previously estimated to take place in 2014. Leading foundries and backend assembly and test service companies have all devoted much of their R&D efforts to TSV development, and are making progress. The major players are believed to be capable of supporting 3D ICs by 2014, but the emerging technology going into commercial production may not take place until around the 2015-16 timeframe."
Probably one of the most interesting presentations at HOPE9, "Indistinguishable From Magic: Manufacturing Modern Computer Chips," covered modern semiconductor fabrication and why these things are cool. If you're interested in more background (what do all of those TLAs mean?), check out the slides / audio (or attached video of the presentation from YouTube).
As we all know, however much They don't want us to, the pace of 'innovation' in semiconductor fabrication is based almost entirely on the reverse engineering of artefacts taken from crashed Grey spacecraft.
Unfortunately, a recent downturn in the tourism sector of Theta Epsilon Minus, caused by the booming popularity of direct neural hedonostimulator technology, has sharply reduced our supply of samples...
Don't care about the latest technology, they will never improve on the technology in Nilla Wafers http://www.nabiscoworld.com/Brands/brandlist.aspx?SiteId=1&CatalogType=1&BrandKey=nilla&BrandLink=/nilla/&BrandId=76&PageNo=1
Uh, it's wafer, not chip, size.
Called D1X (development, but also production like previous "X" fabs) in Oregon, with a second to follow. 450mm wafer production will likely hit volume levels by 2014, just not at the foundries listed in the story.
Price conscious, volume manufacturers like semi foundries would be more willing to push back adoption dates if the investment isn't likely to pay for itself. Most of their business is usually on n-1 or n-2 process nodes. This changeover just happens to be particularly expensive and may not yet make economic sense for another 2-3 years.
The units ARE right. The WAFERs will be 450mm. Today they are 300mm.
It's even more important when you attempt to mock people for wrong units when the units are actually correct.
Um, no. Larger wafers are a cost savings measure. 450mm means that you end up with fewer incomplete chips on the edges of your wafer, which in turn increases your yield. No one is stamping out a single CPU on a 450mm wafer.
You should take this Intel announcement with a big handful of salt. Intel doesn't make the waver producing machinery, they get it from companies like ASML.
Now, there's been a big struggle between companies like Intel that wanted 450mm earlier, and the tool makers who sank a lot of money on the move to 300mm before and don't want to be burned again in the move to 450mm. The Intel announcement above was to put pressure on the tools providers. It didn't worked out in the end.
All this got sorted out between big boys recently, with Intel, TSMC and Samsung investing a lot of money in ASML to speed-up the availability of 450mm. But the accelerated roadmap has nothing to do with the announcement you quote, just look at it from ASML direct (slide 14). The 450mm process development tools are worked on starting mid-2015 and production equipment is available beginning of 2018. Exactly what is said in the TFA.
450mm is important as it is the only known step that will bring the cost of chips down. Other planned changes (finer processes, 3D chips...) increase performance but also cost. But 450mm requires huge upfront investments, so you need large volumes to recoup it and it will require a big upfront spending. Which is why a lot of people are pushing back. Intel has both high volumes, high margins and deep pockets so they're the most eager to get started. But as you can see, even with their backing it's not that simple and fast.
current wafers still yield large numbers of current-sized chips. and for the most part, chip architects are not primarily limited by available area: relentless process shrinks bring, if anything, more transistors than they know how to use. sure, you can always throw on more cache, especially L3. but the main issues today are power and IPC/TLP-type efficiency, not space. the K20 team at NVidia might disagree, but they _should_ be pushing the bounds, since their target is less cost-sensitive HPC, not commodity/gaming.
in short, the action is in litho, process, transistor topology, power and microarchitecture, not the number of chips spoiled by the edges.
Exactly! Why do some people even try and make things better? I mean, are they mental or something? We should gather up all these folks that won't give up and refuse to recognize the futility that is man and shoot them off on a rocket ship to another planet!
I drank what? -- Socrates
Intel's R&D budget alone is around 70% of TSMC's total yearly revenue for example. Also, if you look up rankings of R&D spending by technology companies Intel's is basically the second highest just behind Microsoft.
A standard die is 26x33 mm, which is much larger than the vast majority of the chips; most dies already contain multiple chips. Therefore, the edge loss is not as big a deal as you would think.
What is more of a cost saver is that most of the processing steps (applying photo resist, developing the resist, etching, ion implantation, annealing, and so on) are relatively easy to scale up to larger wafers, thereby reducing the process costs per unit of wafer area.
A big exception here is the lithography process, which gets significantly harder for bigger wafers, since it involves rapidly moving a wafer around with nanometer accuracy. A bigger wafer requires a bigger, stiffer, and therefore heavier wafer stage. ASML manufactures lithography tools that can do up to 175 wafers per hour (300 mm diameter) per hour, with an accuracy ("overlay") of 5.5 nm; that is about 3 dies per second. To give an idea of the scale: imagine that a vehicle is moving at 100 km/h, making multiple sharp turns per second, and tracks the ideal trajectory within 500 nm. And then the customer says: nice that you can do that with a sports car, but it's too small; can you build a heavy SUV that can do the same thing? (So there, a car analogy)
This is why Intel, TSMC, and Samsung have invested into ASML to speed up the development of 450 mm litho tools.
Disclosure: I work for ASML, but the above opinions are my own.
Avantslash: low-bandwidth mobile slashdot.
Exactly! Periodic Table of Elements is complete! The party will be "soon". All forms of propulsion through the air has been figured out. DOD and DOE are cancelling all further ramjet experiments. All you science and engineering students in college? Shoulda' taken Post-Raphelite Literature, loosers!
I drank what? -- Socrates
The lithography is one aspect but what about the deposition/etching equipment? It is spread across multiple vendors and getting them all to support 450mm is going to be one heck of a challenge when for the most part they have only just gotten 300mm production perfected. The chip manufacturers won't/can't settle for 450mm tools that don't hit or exceed the quality of work produced by current 300mm tools because the process nodes now depend on that quality to produce working chips. Maintaining anisotropic plasma etch selectivity or deposition thickness uniformity on over double the area without resorting to much slower processing is going to be a really tough target to hit.
Just because da Vinci came up with the idea of the helicopter hundreds of years ago does not mean we shouldn't have worked atmaking it happen. Sure, some things are more difficult than others but that doesn't mean we should give up. Where would y'all like to live? A world where we only go after low hanging fruit or one where, despite many failures, we keep trying and improve on what we have done before?
Bottom line: On May 31, 2012, the International Union of Pure and Applied Chemistry (IUPAC) approved the addition of flerovium and livermorium to the periodic table of elements. The two new elements were discovered during collaborative research carried out by scientists from the Lawrence Livermore National Laboratory in the United States and the Joint Institute for Nuclear Research in Russia. An official announcement describing the new names of the two elements will be published in the July 2012 issue of the IUPAC journal, Pure and Applied Chemistry.
ScienceDaily (Aug. 16, 2012) — A team of scientists led by Carnegie's Lin Wang has observed a new form of very hard carbon clusters, which are unusual in their mix of crystalline and disordered structure. The material is capable of indenting diamond. This finding has potential applications for a range of mechanical, electronic, and electrochemical uses.
Wright Patterson AFB has confirmed in an official press release that Tuesday’s test of the Waverider X-51A unmanned hypersonic missile has failed. Launched from a B-52 bomber over Point Mugu Naval Air Warfare Center Sea Range at 11:36 AM PST, the separation from the bomber and ignition of the X-51A’s rocket booster went as planned. However, 16 seconds into the flight a fault occurred in one of the missile’s control fins before the scramjet could start, resulting in the craft losing control, and the X-51A was today officially reported as "lost."
I drank what? -- Socrates
The ability of the Twinscan to maintain the positional accuracy that it can at the speeds and accelerations involved is just jaw dropping. I'm sure they are telling you that you cannot do the logical thing to keep the forces manageable by dropping the scan speed much (if any) in the changeover from 300mm to 450mm because everyone would freak out as the whole point is to maximize exposures per second while minimizing wafer exchange time. I do think that other processes will also have some pretty awful trouble getting to 450mm though. Think of all that wafer warping, layer uniformity trouble, and backside contamination!
(former litho overlay engineer, your hard work helped make my vector maps happy)