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Mass Production of 450mm Wafers Bumped Back Again: 2018
Taco Cowboy writes with news on the slipping schedules in the move toward both larger wafers and 3D integrated circuits in the semiconductor fab world. From the articles: "TSMC ... said it planned to start mass-producing next-generation 450mm wafers using advanced 10-nanometer technology in 2018. The advanced 10-nanometer chips could first be used in mobile devices and other consumer electronics, like game consoles, that demand high-performance and low power consumption. The plan was included in the latest technology roadmap unveiled by TSMC about one year after the chipmaker attributed its delay in making 450mm wafers, originally scheduled in 2015, to semiconductor equipment suppliers' postponement in developing advanced equipment for manufacturing amid the industrial slump. Chipmakers can get 2.5 times more chips from a 450mm wafer than from a 300mm wafer ... The industry's gradual migration toward 3D ICs with through-silicon vias (TSV) is unlikely to happen until 2015 or 2016, according to sources at semiconductor companies. Volume production of 3D ICs was previously estimated to take place in 2014. Leading foundries and backend assembly and test service companies have all devoted much of their R&D efforts to TSV development, and are making progress. The major players are believed to be capable of supporting 3D ICs by 2014, but the emerging technology going into commercial production may not take place until around the 2015-16 timeframe."
Probably one of the most interesting presentations at HOPE9, "Indistinguishable From Magic: Manufacturing Modern Computer Chips," covered modern semiconductor fabrication and why these things are cool. If you're interested in more background (what do all of those TLAs mean?), check out the slides / audio (or attached video of the presentation from YouTube).
Called D1X (development, but also production like previous "X" fabs) in Oregon, with a second to follow. 450mm wafer production will likely hit volume levels by 2014, just not at the foundries listed in the story.
Price conscious, volume manufacturers like semi foundries would be more willing to push back adoption dates if the investment isn't likely to pay for itself. Most of their business is usually on n-1 or n-2 process nodes. This changeover just happens to be particularly expensive and may not yet make economic sense for another 2-3 years.
It's even more important when you attempt to mock people for wrong units when the units are actually correct.
Um, no. Larger wafers are a cost savings measure. 450mm means that you end up with fewer incomplete chips on the edges of your wafer, which in turn increases your yield. No one is stamping out a single CPU on a 450mm wafer.
You should take this Intel announcement with a big handful of salt. Intel doesn't make the waver producing machinery, they get it from companies like ASML.
Now, there's been a big struggle between companies like Intel that wanted 450mm earlier, and the tool makers who sank a lot of money on the move to 300mm before and don't want to be burned again in the move to 450mm. The Intel announcement above was to put pressure on the tools providers. It didn't worked out in the end.
All this got sorted out between big boys recently, with Intel, TSMC and Samsung investing a lot of money in ASML to speed-up the availability of 450mm. But the accelerated roadmap has nothing to do with the announcement you quote, just look at it from ASML direct (slide 14). The 450mm process development tools are worked on starting mid-2015 and production equipment is available beginning of 2018. Exactly what is said in the TFA.
450mm is important as it is the only known step that will bring the cost of chips down. Other planned changes (finer processes, 3D chips...) increase performance but also cost. But 450mm requires huge upfront investments, so you need large volumes to recoup it and it will require a big upfront spending. Which is why a lot of people are pushing back. Intel has both high volumes, high margins and deep pockets so they're the most eager to get started. But as you can see, even with their backing it's not that simple and fast.
Exactly! Why do some people even try and make things better? I mean, are they mental or something? We should gather up all these folks that won't give up and refuse to recognize the futility that is man and shoot them off on a rocket ship to another planet!
I drank what? -- Socrates
That's correct for transistor-limited (aka pin-limited) chips, but not so for area-limited chips.
Yes, just like we have CPU-bound software and IO-bound software, we have area-limited and pin-limited chips. Pin-limited chips are where the I/O balls are keeping chips from becoming bigger - you see this as CPUs, SoCs, chipsets and other utility chips (many bus architectures are redesigned to be more conservative on their pin usage - why consume 64 pins when you can use 16).
Area limited chips are where the actual silicon area limits their usage - too big and flaws mean lower yields, too small and your devices may not meet requirements. These kind of devices are typically memory devices - the storage array is the largest consumer of area (the logic fits neatly around it) and the larger you can make the storage array, the bigger the memory.
Memory devices are also some of the most dense, transistor wise (a CPU has tons of "random logic" that means wiring is what keeps transistors spread apart, not transistor density). For a given process node, if you can double the area of the storage array, you double the storage.
And memory devices cover a wide gamut - from imaging devices (CCDs, CMOS), standard DRAMs and SRAMs, and EEPROM-style memory (including flash memory).
Basically the amount of storage you can stick is limited by area (double area, double storage, eseentially), but if you make the area too big, yields go down as the impact of an imperfection destorys the entire chip.
A larger wafer has more area available, and since wafer costs are mostly fixed (a single wafer costs anywhere from $1000-3000 or so), the number of good chips has to pay for it all. The more good chips (higher yield), the cheaper the cost.
A larger wafer means more chips can be made, so cheaper overall memory devices - which translate to cheaper SSDs, cheaper DRAMs, digital cameras with larger sensors, dSLRs with full-frame sensors at a budget price (this one especially - the sensor is the most expensive part because it's genuinely a HUGE piece of silicon and only a handful make it out of a wafer, even allowing for bad pixels).
For other chips, a larger area does allow for more wiring, which is what dominates chip design, not transistors. If you take something like an FPGA - the thing limiting it IS area - wiring area is extremely limited.
A standard die is 26x33 mm, which is much larger than the vast majority of the chips; most dies already contain multiple chips. Therefore, the edge loss is not as big a deal as you would think.
What is more of a cost saver is that most of the processing steps (applying photo resist, developing the resist, etching, ion implantation, annealing, and so on) are relatively easy to scale up to larger wafers, thereby reducing the process costs per unit of wafer area.
A big exception here is the lithography process, which gets significantly harder for bigger wafers, since it involves rapidly moving a wafer around with nanometer accuracy. A bigger wafer requires a bigger, stiffer, and therefore heavier wafer stage. ASML manufactures lithography tools that can do up to 175 wafers per hour (300 mm diameter) per hour, with an accuracy ("overlay") of 5.5 nm; that is about 3 dies per second. To give an idea of the scale: imagine that a vehicle is moving at 100 km/h, making multiple sharp turns per second, and tracks the ideal trajectory within 500 nm. And then the customer says: nice that you can do that with a sports car, but it's too small; can you build a heavy SUV that can do the same thing? (So there, a car analogy)
This is why Intel, TSMC, and Samsung have invested into ASML to speed up the development of 450 mm litho tools.
Disclosure: I work for ASML, but the above opinions are my own.
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The lithography is one aspect but what about the deposition/etching equipment? It is spread across multiple vendors and getting them all to support 450mm is going to be one heck of a challenge when for the most part they have only just gotten 300mm production perfected. The chip manufacturers won't/can't settle for 450mm tools that don't hit or exceed the quality of work produced by current 300mm tools because the process nodes now depend on that quality to produce working chips. Maintaining anisotropic plasma etch selectivity or deposition thickness uniformity on over double the area without resorting to much slower processing is going to be a really tough target to hit.