iPhone 5 A6 SoC Teardown: ARM Cores Appear To Be Laid Out By Hand

MrSeb writes "Reverse engineering company Chipworks has completed its initial microscopic analysis of Apple's new A6 SoC (found in the iPhone 5), and there are some rather interesting findings. First, there's a tri-core GPU — and then there's a custom, hand-made dual-core ARM CPU. Hand-made chips are very rare nowadays, with Chipworks reporting that it hasn't seen a non-Intel hand-made chip for 'years.' The advantage of hand-drawn chips is that they can be more efficient and capable of higher clock speeds — but they take a lot longer (and cost a lot more) to design. Perhaps this is finally the answer to what PA Semi's engineers have been doing at Apple since the company was acquired back in 2008..." Pretty picture of the chip after using an Ion Beam to remove the casing. The question I have is how it's less expensive (in the long run) to lay a chip out by hand once instead of improving your VLSI layout software forever. NP classification notwithstanding.

Comments

Carpal tunnel

[Anonymous Coward]

That must be a very fine tipped resist pen...

Re:Carpal tunnel

[Anonymous Coward]

Yeah I bet their ARMs are tired after making that.

Re:Carpal tunnel

[grcumb]

Wish I had mod points...

Although I'm not sure which way I'd mod you - I laughed and groaned at the same time.

Mod down. Clearly GP is doing more ARM than good.

Re:Carpal tunnel

[mjwx]

Wish I had mod points...

Although I'm not sure which way I'd mod you - I laughed and groaned at the same time.

Mod down. Clearly GP is doing more ARM than good.

Dont you think that's a bit of a RISC

Re:Carpal tunnel

[UnresolvedExternal]

Nop

Costs

[girlintraining]

The question I have is how it's less expensive (in the long run) to lay a chip out by hand once instead of improving your VLSI layout software forever. NP classification notwithstanding.

Coding in assembly still remains a superior method of squeezing extra performance out of software. It's just that few people do it because compilers are "good enough" at guessing which optimizations to apply, and where, and usually development costs are the primary concern for software development. But when you're shipping hundreds of millions of units of hardware, and you're trying to pack as much processing power in a small and efficient form factor, you don't go with VLSI for the same reason you don't go with a compiler for realtime code: You need that extra few percent.

Re:Costs

[pclminion]

Coding in assembly still remains a superior method of squeezing extra performance out of software.

I'd say it's more important to be able to read assembly than to write it. I do a lot of performance optimization of C++ code, and mostly it involves looking at what the compiler generates and figuring out how to change the source code to produce better output from the compiler. Judicious use of const, restrict and inline keywords can make a huge difference, as can loop restructuring (although the compiler can do a fair amount of loop restructuring itself, sometimes it needs help).

It's been a long time since I saw compiler output that made me go "WTF, is this compiler dumb or something?" In fact, it tends to figure things out that are pretty amazing (to me, at least). I once saw a compiler eliminate an entire lookup table which it determined wasn't necessary, an impressive feat of compile-time execution modeling.

Re:Costs

[SageMusings]

You need that extra few percent.

That's why our compilers go to 11.

Re:Costs

[tlhIngan]

But when you're shipping hundreds of millions of units of hardware, and you're trying to pack as much processing power in a small and efficient form factor, you don't go with VLSI for the same reason you don't go with a compiler for realtime code: You need that extra few percent.

The problem with hand-tuned assembly is the same as hand laying out transistors - it gets complicated quickly and if you're not careful, you end up with a horrible mess.

You can argue if you're shipping millions of copies of things, you should hand-tune the code in assembly so it runs the absolute fastest. But there are two costs - programmer timer (development costs) and time to market. There's always one more optimization that can be done. Perfection is the enemy of good.

With VLSI, the same thing applies - you can always reroute/resize transistors and wiring around to squeeze out some more performance out of it. The problem though is the more hand routing you do, the greater the chance of making an error, and often you can miss some transistors or logic. Most of it can be caught during schematic checks, but there's a very good chance of missing out logic blocks in the schematics and ending up with bugs. Or you can miss an extra body contact and end up with very odd bugs.

Then there's trying to fit it in the floorplan - and there's always a wire that won't fit in the space. You're dealing with probably close to a million transistors, after all.

Chip design not black-or-white

[whoever57]

Today, chips are nearly always laid out using advanced, CAD-like software â" the designer says he wants X cache, Y FPUs, and Z cores, and the software automagically creates a chip. Hand-drawn processors, on the other hand, are painstakingly laid out by chip designers.

There are a lot of layout methodologies that are between the (frankly mythical) "X cache, Y FPUs, and Z cores" and fully hand layout. The top level may have more or less amounts of hand assembly, some blocks can be hand optimized, etc.. Usually, there is lots of glue logic which must be designed in RTL, synthesized and only then laid-out. And, for most blocks the process to create the logic design (RTL or perhaps gates) is separate from the process of laying-out these blocks. So there is room for manual involvement in each of the steps.

Why assembly ...

[perpenso]

The question I have is how it's less expensive (in the long run) to lay a chip out by hand once instead of improving your VLSI layout software forever. NP classification notwithstanding.

Coding in assembly still remains a superior method of squeezing extra performance out of software. It's just that few people do it because compilers are "good enough" at guessing which optimizations to apply, and where, and usually development costs are the primary concern for software development. But when you're shipping hundreds of millions of units of hardware, and you're trying to pack as much processing power in a small and efficient form factor, you don't go with VLSI for the same reason you don't go with a compiler for realtime code: You need that extra few percent.

I like to view things as a little more complicated than just applying optimizations. IMHO assembly gets some of its biggest wins when the human programmer has information that can't quite be expressed in the programming language. Specifically I recall such things in the bad old days when games and graphics code would use fixed point math. The programmer knew the goal was to multiply two 32-bit values, get a 64-bit result and right shift that result back down to 32 bits. The Intel assembly programmer knew this could be done in a single instruction. However there wasn't any real way to convey the bit twiddling details of this fixed point multiply to a C compiler so that it could do a comparable operation. C code could do the calculation but it needed to multiply two 64-bit operands to get the 64-bit result.

Re:Why assembly ...

[swillden]

I don't know what that single instruction would be (I am not an assembler expert), or how likely it is that a compiler would recognize it.

Followup: Just for fun I decided to test it. I compiled the code with -O1 on my handy compiler (g++ 4.6.3) and what it produced was:

imulq %rdi, %rax
shrq $32, %rax

So, two instructions. However, it occurred to me that perhaps the code in question was to be run on a 32-bit processor, and my compiler is compiling for 64 bits. So I changed the problem a bit, to the analogous one on a 64-bit CPU:

uint64_t((__uint128_t(a) * b) >> 64)

and what the compiler produced was:

mulq %rdi

So, it looks like gcc 4.6.3 does, in fact, recognize how to optimize this particular code. No need for inline assembler here.

Looking closely

[taniwha]

Looking closely I see a bunch of ram - probably half laid out by hand (caches) - and a many may small standard cell blocks almost certainly not laid out by hand - what I don't see is an obviously hand laid out datapath (the first part of your CPU you spend layout engineers on) - look for that diagonal where the barrel shifter(s) would be. There are some very regular structures (8 vertically) that I suspect are register blocks.

Still what I see is probably someone managing timing by synthesizing small std cell blocks (not by hand), laying those blocks out by hand then letting their router hook them up on a second pass - - it's probably a great way to spend a little extra time guiding your tools into doing a better job to squeeze that extra 20% out of your timing budget and give you a greater gate density (and lower resulting wire delays)

So - a little bit of stuff being done by hand but almost all the gates being lait out by machine

Re:Site is down

[sexconker]

I've put the picture (which is what everyone wants) up here:
http://i.imgur.com/vqCAu.jpg

'by hand' - not really.

[queazocotal]

This is not by hand.
To take a programming analogy, it's looking at what the compiler generated, and then giving it hints so the resultant code/chip is laid out as you expect.

Chips stopped being able to be laid out 'properly' by hand some time ago.

Doing this has much the same benefits as doing it with code.
You know stuff the compiler does not.
You can spot silly stuff it's doing, that is not wrong, but suboptimal, and hold its hand.

Re:'by hand' - not really.

[Sulphur]

This is not by hand.
To take a programming analogy, it's looking at what the compiler generated, and then giving it hints so the resultant code/chip is laid out as you expect.

Chips stopped being able to be laid out 'properly' by hand some time ago.

Doing this has much the same benefits as doing it with code.
You know stuff the compiler does not.
You can spot silly stuff it's doing, that is not wrong, but suboptimal, and hold its hand.

Or grab its ARM.

It's a level of indirection

[Kjella]

The question I have is how it's less expensive (in the long run) to lay a chip out by hand once instead of improving your VLSI layout software forever.

You can teach a small kid to ride a bicycle. The same kid has no chance to program a robot into doing the same motion and balancing. It's the same order of magnitude in difference with VLSI layout, a person can lay out the circuits but it's almost impossible to describe to the computer all the reasons why he'd lay it out that way. It's not easy controlling anything well through a level of indirection, that's true for most things.

As for being "less expensive", companies don't just have expenses but they have income too. If you can increase revenue because you got a better chip that sells more, they're willing to pay a higher cost. Companies care about profits, not expenses in isolation. Those tiny improvements to the compiler, how valuable are they to Apple in 10 years? 20 years? As opposed to an optimized chip which they know how much is worth right now.

Re:A6 hand layout awesome performance sweet

[Anonymous Coward]

Android users usually get laid by hand.

News For This Nerd

[History's Coming To]

Brilliant, this is what I love about Slashdot, I can be the biggest geek in whatever field I pick and I will still get outgeeked! I enjoyed reading the comments above mostly because I have absolutely no idea what the detail is, and I'd never even realised that hand-drawn vs machine was a issue.

Can anyone supply a concise explanation of the differences and how it's all done? I'm guessing we're talking about people drawing circuits on acetate or similar and then it's scaled down photo-style to produce a mask for the actual chip?

Yes, I know I can just Google it, and I will, but as the question came up here I thought I'd add something to a real conversation, it beats a pointless click of some vague "like" button any day :)

Re:News For This Nerd

[oji-sama]

Sorry, not an expert, but you might find this article (about AMD Steamroller) interesting. At least check the short "Looking Forward: High Density Libraries". They are rebuilding hand-drawn diagrams to be more efficient. http://www.anandtech.com/show/6201/amd-details-its-3rd-gen-steamroller-architecture/2

Re:News For This Nerd

[lexman098]

The headline is attention-grabbing bullshit.

I'd believe that Intel may have in the past done manual placing and routing of custom made cells in certain key parts of their CPUs, but I can almost assure you that Apple did not place all of the standard cells in their ARM core's and then route them together manually, which is what the headline implies.

What I'm talking about here is literally placing down a hundred thousand rectangles in a CAD tool and then connecting them correctly with more rectangles which is way beyond what Apple would have considered worth the investment for a single iPhone iteration. What's more probable (and pretty standard for digital chip design) is that they placed all of the large blocks in the chip by hand (or at least by coordinates hand-placed in a script), and they probably "guided" their place and route tool as to which general areas to place the various components of the ARM cores. They might have even gone in after the tool and fixed things up here and there.

Modern chips are almost literally impossible to "lay out by hand".

Re:News For This Nerd

[slew]

Nobody "draws" chips by "hand" anymore. It's all being done by a computer (there are so many design rules these days humans can't do this anymore in a realistic time frame). Reticles (the photomasks) are all fractured by computer these days because rectangles aren't really rectangles anymore at these small feature sizes (we are now past the diffraction limit so masks must be "phase-shift" masks not binary masks back in the old-days).

I don't have any specific knowledge about the A6, but what is euphamistically called hand-drawn these days is often still very automated relative to the bad-old-days when people were drawing rectangles on layers to make transitors. That was the real-hand-drawn days, but even way back then you didn't actually draw them by hand, you used a computer program to enter the coordinates for the rectangles.

Quick background: now days when typical chips go to physical design, they usually go through a system called place-and-route where pre-optimized "cells" (which have 2-4 inputs and 1-3 outputs and implement stuff like and-or-invert, or register flop) are placed down by the computer (typically using advanced heuristic algorithms) and the various inputs and outputs are connected together with many layers of wires which logically match the schematic or netlist (which is the intention of the logical design). Of course this is when physics starts to impose on the "logical" design, so often things need special fixups to make things work. Unfortunatly, the fixups and the worst case wirelengths between cells conspire to limit the performance and power of the design, but just like compiled software, it's usually good enough for most purposes. Highly leveraged regularly structured components of normal designs might have libraries, specialized compilers or even have hand intervention (e.g, rams, fifos, or register files), but not the bulk of the logic.

As far as I can tell from looking at the pictures the most likely possibility is that just that instead of letting the computer place the design completely out of small cells, some larger blocks (say like ALUs for the ARM SIMD path) were created by a designer and layout engineer who probably used a lower-level tool to put down the same small cells relative to other small cells where they think is a good place to put them and tweak the relative positioning to try to minimize the maximum wire lengths between critical parts of the block. The most common flow for doing this is mostly automated, but tweakable with human intervention (this what passed for "by-hand" these days). In addition to being designed to optimize critical paths, these larger blocks are generally desgined so that they "fit" well with other parts of the design (e.g., port order, wire pitch match, etc) to minimize wire congestion (so they can be connected with mostly straight wires, instead of those that bend). Basically looking at the patterns of whitespace in the presumed CPU, you can see the structure of these larger blocks instead of big rectangles (called partitions) which have rows of cells you get when you let a computer do place-and-route with small cells.

Just like optimizing a program, there are many levels of pain you can go through and what I described above is probably the limit these days. Say if you wanted less pain, another more automated way to get most of the same benefits is to just develop a flow that hints where to put parts of the design inside the normal rectangular placement region, and let a placement engine use those hints. The designer can just tweak the hints to get better results. Of course with this method, the routing may still have "kinks" in this case because routing is not wire-pitch-matched, but you can often get 80-90% the way there. The advantage of this lesser technique is that you don't need to spend a bunch of time developing big blocks and if there is a small mistake (of course nobody ever makes mistakes), it's much, much easier to fix the mistake w/o perturbing the whole design.

FWIW, it is highly unlikely that th

Re:Site is down

[thammoud]

Yup. That definitely is hand made.

Automation is the win for *some* tasks

[perpenso]

...companies thinking in the long run prefer an intelligent or well-trained workforce to automation and minimum wage.

In general your point does have some merit but it really does depend on the specific task at hand. My grandfather was a master welder. However for *some* of the tasks that he used to perform a robotic welding system would be a better idea.

lets look at a different analogy

[v1]

I don't think bicycle riding is a very good analogy to this problem. How about cooking, which is a procedural step-by-step operation? Little hints the recipe can give you like "preheat oven to 350 degrees" can be a tremendous time-saver later. If you didn't know to do that, you'd get your dish ready and then look at the oven (off) and click it on and sit back and wait 20 minutes before placing it in the oven. A dish that was supposed to be 60 minutes start to serve is now going to take 80 minutes due to a lack of process optimization.

Compilers have the same problem of not knowing what the expectations are down the road, and aren't good at timing things. Good expereinced cooks can manage a 4 course meal and time it so all the dishes are done at the right time and don't dirty as many dishes. Inexperienced cooks are much like compilers, they can get the job done but their timing and efficiency usually have much room for improvement.

Re:lets look at a different analogy

[mspohr]

I think we need a car analogy.
Following iLost maps while drunk driving is like using a compiler.
On the other hand, following the directions from your mother in law in the back seat is like a fish.
YMMV

Re:Site is down

[busyqth]

Actually not only is that one hand made, each and every A6 is lovingly hand made. That's why they're top quality.

Re:Site is down

[lister king of smeg]

and their tech section is run by taco so it could be counted as a sort of pseudo-slashdot effect they have as well

Re:Hand-drawn chips really better?

[busyqth]

it's 2012, haven't intel or amd engineers developed algorithms to do the chip design for them?

No, they never thought of doing that. Hurry up and apply for the patent.

Re:What makes hand-made chips "faster"?

[Hatta]

I'm guessing that the search space is too large to brute force the optimization. For similar reasons we can't write a program that can beat a Go master. It's just too hard a problem without heuristics, and the heuristics in the human brain are better. Figure out why, and you've solved AI.

Re:What makes hand-made chips "faster"?

[marcansoft]

What you're missing is that chip layout is NP-complete. For anything beyond very trivial chips, no computer algorithm can yield the optimal solution in a reasonable time.

As I understand it, automated layout algorithms are still, when you get down to it, largely quite dumb. I'm sure this is oversimplifying and someone who writes place-and-route software will probably want to kill me, but the algorithm is closer to "throw stuff together, measure performance, tweak things randomly, measure performance, keep the change if it got better" than to anything likely to yield an optimal solution. Eventually, you'll converge on a decent layout, sure, but not an optimal one.

It's pretty much guaranteed that this chip wasn't completely hand-crafted (modern chips are much too complicated to do that). Instead, most likely, engineers guided the placement of major blocks and data paths, and let the automated place-and-route software choose the rest. By constraining the design based on intelligent decisions, you can guide the automated process to converge on a better solution.

Layout by HAL

[Anonymous Coward]

" The question I have is how it's less expensive (in the long run) to lay a chip out by hand once instead of improving your VLSI layout software forever. NP classification notwithstanding."

I've done PCB layouts, microwave chip and wire circuits, as well as RFIC/MMIC layouts. Anyone who asks the question above has never done a real layout. Many autorouter and layout tools allow complex rules to match delays, keep minimum widths, etc. You can spend as much time on each layout trying to populate these rules for critical sections of a design, but it is like trying to train a 5 year old to do brain surgery. Digital design is rather much different than the analog circuits I work on, but you only have to do a few layouts of any flavor by hand in your life to be able to see just how scary it is to hand a layout to HAL.

Clearly autorouters and autogenerated layouts, and I don't mean to sound like too much of a luddite... I've witnesses plenty of awful hand layouts to go around as well.

Re:And made by Samsung

[Lunix Nutcase]

Display is LG, Flash is Hynix, the RAM is from Elpida and their chip is their own design with Samsung just acting as a fab no different than Global Foundries or TSMC.

Re:Apple...

[busyqth]

Seing those guys evolve is like watching an intricate ballet while everybody else is sumo wrestling.

So are you calling Apple users effeminate?

Re:Site is down

[Lumpy]

But they are not lovingly hand made on the thighs of Virgins... That is reserved for El Presidente' Processors.

Re:What makes hand-made chips "faster"?

[AK Marc]

And an incremental chip would benefit from hand-holding more than a new one. Say they tested the chip at + 50% clock speed and identified locations of instability. Then, they "by hand" took an optimized automated layout and tweaked it to improve those few specific areas. That would be a "by hand" design that didn't take too much work and gave a better result. Perhaps do the same thing, but with 50% less voltage, rather then increased speed. Then hand-optimize on that. Then compare the two and come up with something that's faster and lower power than the automated process would ever come up with.

Most algorithms I've messed with are very good at iteration, but bad at evolution (they win chess by calculating odds and values, not by analyzing the opponent and his moves).

Re:And made by Samsung

[busyqth]

Display is LG. Flash is mostly Hynix and Toshiiba.

Yeah, but the software is Samsung, and everyone knows that's what really counts.

The CPU is manufactured by Samsung, and that's what really counts for Fandroids.

Nah, I was referring to the well sourced fact that iOS is actually just a gimped version of Android.
Remember Schmidt was on the Apple board, and he provided preview copies of Android to Jobs.

Re:Hand-made?

[Type44Q]

They're made into nutritional supplements that you can pick up in a rectangular bar form

With rounded corners?

ARM hard blocks are always laid out by hand...

[Wierdy1024]

When someone buys a design from ARM, they buy one of two things:

1. A Hard macro block. This is like an mspaint version of a cpu. it looks just like the photos here. The CPU has been laid out partially by hand by ARM engineers. The buyer must use it exactly as supplied - changing it would be neigh-on impossible. In the software world, it's the equivalent of giving an exe file.

2. Source Code. This can be compiled by the buyer. Most buyers make minor changes, like adjusting the memory controller or caches, or adding custom FPU-like things. They then compile themselves. Most use a standard compiler rather than hand-laying out the stuff, and performance is therefore lower.

The articles assertion that hand layout hasn't been done for years outside intel as far as I know is codswallop. Elements of hand layout, from gate design to designing memory cells and cache blocks have been present in ARM hard blocks since the very first arm processors. Go look in the lobby at ARM HQ in Cambridge UK and you can see the meticulous hand layout of their first cpu, and it's so simple you can see every wire!

Apple has probably collaborated with ARM to get a hand layout done with apples chosen modifications. I can't see anything new or innovative here.

Evidence: http://www.arm.com/images/A9-osprey-hres.jpg (this is a layout for an ARM Cortex A9)

Re:ARM hard blocks are always laid out by hand...

[Lunix Nutcase]

When someone buys a design from ARM, they buy one of two things:

Which is not what Apple did.

Apple has probably collaborated with ARM to get a hand layout done with apples chosen modifications. I can't see anything new or innovative here.

No, they designed it themselves since they are an architectural licensee like Qualcomm. You remember how they bought PA Semi?

Automation versus human instinct

[Taco Cowboy]

The question I have is how it's less expensive (in the long run) to lay a chip out by hand once instead of improving your VLSI layout software forever.

No matter how much improvement on VLSI layout software their output can't match that of hand-laid layout by those who know what they are doing.

The VLSI layout software are like compilers. The final compiled code relies on two factors - the source-code input and the built-in "rules" of the compilers.

A similar case is in software programming - The source code from a so-so programmer compiled by a very very good compiler will result in a "good-enough" result.

It's good enough because it gets the job done.

However, a similar program by an expert Assembly Language programmer would have left "good enough" behind because the assembly language programmer would know how to tweak his code using the most efficient commands, and cut out the 'fats" by optimizing the loops and flows.

Re:Automation versus human instinct

[CastrTroy]

I think you underestimate how good compilers have become. Also, the "expert assembly language programmer" probably would work at 1/100 the pace of a programmer in something more high level like C++. It would probably be next to impossible to write an entire modern operating system, web browser, or word processor in assembly language. Sure for some very small sections of code you can optimize at the assembly level, but you can't write a whole program in assembly. Also, if a person can recognize some optimization, then that optimization can be added to the compiler, which means that a compiler can probably always at least come within a very close margin of where the human could get, and it could probably do better, because a compiler can remember a lot more optimizations than any human can.

Re:Automation versus human instinct

[Taco Cowboy]

I think you underestimate how good compilers have become

Nope.

I know how good compilers have become - especially compilers from the makers of the particular processor the program supposed to be run on.

But I guess you may have missed the "so-so programmer" I've mentioned.

Even the top-line compiler can't produce a top-notch program if been fed source code by a so-so programmer.

There are a lot of ways to write programs.

From the so-so programmers, the source code read like a bowl of bland noodles.

But from a top-notch programmer, he or she would know how to structure his/her program in such a manner similar to what a top-notch chef can get out of a bowl of bland noodles.

Re:Automation versus human instinct

[hazydave]

Well, the real answer is that it's not an either/or scenario. Chip design teams design and layout chips based on off-the-shelf tools, layout expertise, etc. Silicon compilers are also constantly improved, but a completely different set of people are involved. Not sure about today's Apple, but the 80s/90s Apple probably would have done it both ways. In fact, even now I think about it, and the way the Intrinsity guys seem to work, it makes sense.

This is sometimes done in PCB layout. Sure, some types of layout, like RF, are pretty much always done by hand. Today's successful autorouters work from a large set of design constraints that describe the circuit at a high level. You may get a layout sufficient fir a prototype in a week rather than the month the hand layout would take. On a tight schedule, that's two free weeks of bring up.

So it might well be that they ran the silicon compiler, tweaked and simulated the piss out of the design, in parallel with the much longer hand layout. Maybe a bit like hand optimizing compiled code with downcoding/recoding and profilers.

As for hand layout/coding always beating compilers, not in practice. One is certainly a time constraint... the compiler will produce a better end product below a certain time limit. Just where that line is drawn depends on the coder and the complexity of the process. As the CPU/PCB/chip rule sets grow, the compiler does better than the human, assuming it can efficiently factor in the rule set. Naturally, when it can't, you need the personal touch. Until it's expanded to embrace the new rules...like vector or GPGPU coding today. The other factor is of course architecture .. human time is usually better spent on the big picture items, architecture and algorithm. No sense hand coding for a 10% improvement in quality when the same time spent on design might yield 100%.

Not to mention the JIT factor -- code is compiled on the fly for the specific CPU and system in use. Custom DSP pipelines created based on the problem at hand. A complex math problem is targeted,on the fly, to somewhere between 32 and 4096 parallel processing elements. Compilers always win here.

Re:Automation versus human instinct

[Pseudonym]

I think you underestimate how good compilers have become.

I think you may have misunderstood the realities of what a modern expert assembly language programmer does.

An expert assembly language programmer knows when to write assembly language and when not to write assembly language. Assuming that raw performance is the metric by which programmers are judged (which isn't necessarily the case), an expert assembly language programmer will still win over any high-level language programmer because they can also use the compiler.

It's the same with hand-laid-out VLSI. It's not like some team of hardware designers placed every single transistor. That would cause just as much of an unmaintainable mess as writing a large application entirely in assembly language. Rather, the hand-layout designer worked in partnership with the automated tools.

Re:Automation versus human instinct

[the_humeister]

It would probably be next to impossible to write an entire modern operating system, web browser, or word processor in assembly language.

Here you go. It's pretty impressive for something written entirely in assembly .

Re:Automation versus human instinct

[TheRaven64]

Compilers almost always do a much better job than humans if provided with the same input. The advantage that humans have is that they are often aware of extra information that is not encoded in the source language and so can apply extra invariants that the compiler is not aware of. A human is also typically more free to change data formats, for example for better cache usage, whereas a compiler for a language like C is required to take whatever layouts the programmer provided.

The problem with place-and-route is that the search space is enormous and automated tools typically use purely deterministic algorithms, whereas humans use a lot more backtracking. A simulated annealing approach, for example, can often do a lot better (check the literature, there are a few research systems that do this).

However, a similar program by an expert Assembly Language programmer would have left "good enough" behind because the assembly language programmer would know how to tweak his code using the most efficient commands, and cut out the 'fats" by optimizing the loops and flows.

This is, on a modern architecture, complete bullshit. Whoever is generating the assembly needs to be aware of pipeline behaviour, the latency and dispatch timings of every instruction and equivalences between them. Even if you just compare register allocation and use the same instruction selection, humans typically do significantly worse than even mediocre compilers. Instruction selection is just applying a (very large) set of rules: it's exactly the sort of task that computers do better than humans.

Re:Automation versus human instinct

[stevew]

Okay - I'm stepping in here because I actually do chip design for a living. The difference between hand laid-out and machine generated chips can be as much as a 5X performance difference. The facts are that physical design isn't the same as compiler writing. It's a harder problem to crack - first it's a multi-dimensional problem. Next, it has to follow the laws of physics, themselves complicated ;-)

Both processes DO rely on the quality of input. When my designs don't run fast enough, the likely fix is to go back to the source and fix it there instead of trying to come up with some fix within placement and routing. The other simple fact is that in timing a physical design - you have to consider EVERY path that the logic takes in parallel. There is not such thing as the "inner-most" loop of the algorithm for determining where the performance goes. Finally once you have a good architecture for timing, the placement of the physical gates dominates the process.

A human - with their common sense is always going to give better performance than an algorithm. I mentioned a 5X difference between hand-drawn & compiled hardware. That is about what I see on a daily basis between what my tools can do for me, and what Intel gets out of their hand-drawn designs for a given technology node.

Re:Automation versus human instinct

[Theovon]

I'm a chip designer too (although probably not as good as you are), and one thing I wanted to mention for the benefit of others is that in today's chips, circuit delays are dominated by wires. It used to be dominated by transistor delays now, but today, a long interconnect in your circuit is something to avoid at all costs. So careful layout of transistors and careful arrangement of interconnects is of paramount importance. Automatic layout tools use AI techniques like simulated annealing to take a poorly laid-out circuit and try to improve it, but they're even now still poor at doing placement while taking into account routing delays. Placement and routing used to be done in two steps, but placement can have a huge effect on possible routing, which dominates circuit delay. Automatic routers try to do their jobs without a whole lot of high-level knowledge about the circuit, while a human can be a lot more intelligent about it, laying out transistors such with a better understanding of the wires that will be required for that gate, along with the wires for gates not let laid out.

Circuit layout is an NP-hard problem, meaning that even if you had the optimal layout, you wouldn't be able to determine that in any simple manner. Computers use AI to solve this problem. There is no direct way for a computer to solve the problem. So until we either find that P=NP or find a way to capture human intelligence in a computer, circuit layout is precisely the sort of thing that humans will be better at than computers.

Compilers for software are a different matter. While some aspects of compiling are NP-complete (e.g. register coloring), many optimizations that a compiler handles better are very localized (like instruction scheduling), making it feasible to consider a few hundred distinct instruction sequences, if that's even necessary. Mostly, where compilers beat humans is when it comes to keeping track of countless details. For instance, with static instruction scheduling, if you know something about the microarchitecture of the CPU that informs you about when instruction results will be available, then you won't schedule instructions to execute before their inputs are available (or else you'll get stalls). This is the sort of mind-numbing stuff that you WANT the computer to take care of for you. Compilers HAVE been getting a lot more sophisticated, offering higher-level optimizations, but in many ways, what the compiler has to work with is very bottom-up. You can get better results if the human programmer organizes his algorithms with knowledge of factors that affect performance (cache sizes, etc.). There is only so much whole-program optimization can do with bad algorithms.

Interestingly, at near-threadhold voltages (an increasingly popular power-saving technique), circuit delay becomes once again dominated by transistors. When lowering supply voltage, signal propagation in wires slows down, but transistors (in static CMOS at least) slow down a hell of a lot more.

Re:Automation versus human instinct

[Pseudonym]

I'm not a hardware designer (obviously), but I am a compiler writer by trade, and I have put in a bit of research in the current literature of VLSI design, and share a commute with a VLSI designer with whom I talk about this stuff all the time.

My assessment, which is worth exactly what you paid for it, is that while I agree that VLSI design isn't the same as compiler writing, I'm not convinced that it's necessarily a harder problem. To be clear, I'm not trying to get into a pissing contest here. My conjecture is that the "big" problems are of about equal difficulty, but more brain-hours have been dedicated to researching compilers than researching VLSI design tools.

That's largely because of the volume of research material. There is, by line-of-code, far more software than hardware in the world, and more people use compilers than VLSI design tools. And, of course, there's more production-quality software source code available to researchers than there is for hardware. AMD does not simply release its netlists to anyone who asks.

And then there's the return-on-funding-investment issue: software research directly benefits a lot more organisations than hardware research. Yes, we would all be better off with faster-time-to-market hardware, but until quite recently, basic research in VLSI tools would mostly directly benefit the bottom lines of Intel and NVIDIA, where basic research in software tools would directly benefit the bottom lines of startups everywhere.

There's also the problem of turn-around time. The turn-around time for testing a software artefact can be measured in seconds or minutes, where testing a hardware artefact may take days or longer. Even if we started at the same point in history and dedicated the same number of researchers to the problem, compilers would quickly ahead faster than hardware would simply because of the time it takes to run a single experiment! For software, compilation is manufacturing.

So that's why I think there's an apparent discrepancy. Now here's why I think the underlying problems are similar:

First off, from a theoretical point of view, most of the subproblems of interest in both areas are NP-hard. Of course, that could be why they're "of interest".

Now, of course, it's not true that NP-hard problems are all alike in practice, even though they are in theory. For some NP-hard problems (SAT modulo theories being the obvious example), it's tractable to solve them exactly even for quite large problem sizes. For others, we can't even get decent solutions to moderate-sized problems. Some problems feature pretty good known heuristics, where others do not. the heuristics used by compiler writers develop at a faster rate.

Secondly, to the extent that problems of interest are not NP-hard, they seem to be just too different to make a fair comparison.

For example, it is true that some of the physics constraints (e.g. parasitic capacitance) do not have good models which you could just slot into an existing constraint solver. I find it hard to believe that this is because the problem is inherently more complicated than the deep-magic-on-the-global-properties-of-the-program that some modern compilers do. It's far more likely that the right sort of people simply haven't gone to the trouble to try to understand them.

Hell, at least problems like that are actually solvable in principle! Compilers try to understand Turing-complete languages, so some of those problems are inherently unsolvable.

Re:Fixed point multiply

[gr8_phk]

The proper syntax for that is (using x64 types) something like:

int a,b,z;

z = (int)(((long long)a * b) >> 32);

I'm assuming int is 32bit and long long is 64. Even though a is promoted to a larger type and also b, good compilers know that the upper half of those promoted variables are not relevant. They will then use the 32bit multiply, shift the 64bit result and store the part you need. I still do fixed point for control systems and find using 16bit signals and 32bit products is faster in C than floating point even on some embedded PPC chips - never mind the fixed point DSPs we use where the shifts cost nothing. Anyway, this syntax also worked on a HC12 compiler back in '98 or so. It's still hit or miss, but generally works on parts where this stuff is still common.

Re:What makes hand-made chips "faster"?

[gr8_phk]

A compiler analogy. Until recently, register allocation was a hard problem better handled by human experts. Now there are polynomial time algorithms for handling it and compilers can do it optimally. I imagine the subtleties of layout make it a much harder problem to automate - similar to the difference between chess and go.

Re:What makes hand-made chips "faster"?

[Anonymous Coward]

>> automated layout algorithms are still, when you get down to it, largely quite dumb

Auto-custom layout tools are rare, good ones are usually shaped like humans.

Change 'layout' to 'placement' and I fully agree. Leave it as 'layout' and change 'dumb' to 'nearly non-existent' and I agree again. Good layout people are worth gold, they are two steps from the GDSII stream and they build working circuits from a spice deck or w/e gibberish the circuit designer dumps on them. I'm not a layout person, they just are the difference between making it work and yet another great idea.

>> It's pretty much guaranteed that this chip wasn't completely hand-crafted

Yes, agree, but this concept of by-hand is relative, by-hand back in the day was walking around in a giant room drawing transistors on sheets of the moral equivalent of mylar. Yes I was there...

Fast forward to where we have computers and cool-ish stuff: cpu houses usually break logic into 3 mushy categories, random logic synthesis (RLS), structured datapath (SDP) and full custom.

Recognizing RLS from a picture is pretty easy, blob of standard cells apparently randomly placed.

The differences between SDP and full custom (in the obviously not RAM areas) are tougher to distinguish in these pictures, not enough detail in the images and difficult to tell what is actual layout and what are effects of the post-mortem process.

SDP is a manually intensive process, but not nearly time consuming as full custom since you are still primarily dealing with a standard cell library and not 'rolling your own'. The visual effect is similar to full custom, regular patterns easy for the eye to distinguish.

But I am surprised by the amount of apparent white space in the pictures, which is an indirect indicator of custom blocks stitched together after their individual design is complete, typically not the case in SDP (nor obviously RLS).

So that really begs a much larger question. If it is a custom design why the hell go through all the trouble and then lose a chunk of the benefit by placing these lovingly crafted blocks in such a way? This is money, more importantly power consumption efficiency left on the table. I'm not judging but more wondering about the tradeoff choices made, could be tech, could be schedule, too far away to judge.

Working backwards from product announce, having some idea about how long this takes, full custom or SDP/custom mixture, this could be the work of that crufty crew at Intrinsity (quondam notus ut EVSX, Exponential Technology) who (apparently) did the previous work on Apple A5 in the Samsung process. The calendar time works out.

Re:What makes hand-made chips "faster"?

[Space cowboy]

As a mathematician, you ought to understand global optimization encountering local minima in a high-dimensional space. Standard tools for large-scale functional minimization are all subject to it in one form or another, and humans get to ignore all the "stuff that doesn't make sense" - machines don't have that latitude, at least with current algorithms.

Don't get me wrong, the layout and design tools are on the bleeding edge; they're as sophisticated as they come, and there's a *huge* amount of maths in how they work, but they're still crap, compared to a moderately skilled human. What they do excel at is doing all the tedious repetitive work that is typically required, and there's a *lot* of that.

Simon

Re:And made by Samsung

[Anonymous Coward]

This article about Apple (and Qualcomm) wanting to use TSMC came out a few days after the verdict.

Huh?

[Panaflex]

Not surprising at all, as PA SEMI was founded by Daniel W. Dobberpuhl.

Daniel Dobberpuhl had his hand in StrongARM and DEC Alpha design - both hand-drawn cores which to this day command some respect in chip design circles I'm told.

Anyway,

Looks like a modern semi-custom chip to me

[Brannon]

I don't see anything in the pictures which implies "hand custom layout". I see a lot of carefully placed and floorplanned blocks, some of which are synthesized and some of which may have varying degrees of directed placement & routing. There are a lot of RAMs and register files, which look very regular but there's no way to tell whether they were generated by a bog standard RAM/RF compiler or whether there was some custom work (perhaps a combination of the two). There are a lot of unique blocks for a chip this size, I suspect there are several fixed function units to do various things (mpeg decoding or whatnot).

Hand custom layout conjures images of dozens of layout engineers drawing polygons for every transistor; I doubt they did much of that but I'm certain you can't tell from these kinds of photos.

It certainly looks "designed" and knowing how sharp the pasemi folks are then that isn't at all surprising.

result on gcc 4.5.1

[Chirs]

Looks like gcc isn't a good compiler.
Compiling this at -O3

int mult(int a, int b)
{
        return (int)(((long long)a * b) >> 32);
}

In x86-64 mode gives

movslq %esi, %rax
movslq %edi, %rdi
imulq %rdi, %rax
sarq $32, %rax
ret

and 32-bit mode gives

pushl %ebp
movl %esp, %ebp
movl 12(%ebp), %eax
imull 8(%ebp)
popl %ebp
movl %edx, %eax
ret

On powerpc the 64-bit version is very clean and obvious:

mulld 4,4,3
sradi 3,4,32
blr

the 32-bit version is a little bit more complicated

mulhw 9,4,3
mullw 10,4,3
srawi 11,9,31
srawi 12,9,0
mr 3,12
  blr

The arithmetic is simple

[dbc]

The question I have is how it's less expensive (in the long run) to lay a chip out by hand once instead of improving your VLSI layout software forever. NP classification notwithstanding.

It's simple math. At what volume will the chip be produced? A modern fab costs $X Billion, and you know pretty much exactly how many wafers you can run during the 3 years it is state-of-the-art. After that, add $Y Billion for a refit, or just continue to run old processes. Anyway, say a new fab at refit time would cost $Z Billion. Refitting the old fab instead costs $Y Billion. So you save $Z-$Y by doing a refit. So the original fab cost you $X-($Z-$Y). Divide by number of wafers the fab can run during its life, that is the cost per wafer. Now compute die area for hand layout versus auto layout, and adjust for imporved yield for smaller die. Divide by die per wafer. That is how much less each die costs you. Now since the die is smaller, it probably runs faster, so adjust your yield-to-frequency-spec upwards, or adjust your average selling price upwards if the speed difference is "large" (enough MHz to have marketing value). That is the value of hand layout. It isn't rocket surgury to work out a dollars-and-cents number.

Anyway, even at Intel for at least the past 20 years only highly repetive structures like datapath logic has been hand laid out. Control logic is too tedius to lay out by hand, doesn't yield much area benefit, and is where the bulk of the bug fixes end up so it's the most volatile part of the layout from stepping to stepping.

So, can hand layout have a positive return on investment? Yes, if you run enough wafers of one part to make the math work out. These days the math will only work out for higher volume parts.

(Yes, I'm ex-Intel).