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IBM Reports Carbon Nanotube Chip Breakthrough
First time accepted submitter yawaramin writes "IBM has apparently made a breakthrough in arranging carbon nanotubes into the logic gates necessary to make a chip. This should help miniaturize and speed up processors beyond what today's silicon-based technologies are capable of. The article notes though that perfecting the carbon nanotube technology could take up the rest of this decade."
Most stories I see say that [insert favourite research here] will be ready for commercial production within five years. Finally, somebody's being honest and saying it won't be ready before the end of this decade.
for the wife. Now she can vacuum and have some logic. Assuming the tube is large enough.
The IBM research paper is available at http://www.nature.com/nnano/journal/vaop/ncurrent/full/nnano.2012.189.html The paper is protected by a paywall.
The IBM press release is available at http://www-03.ibm.com/press/us/en/pressrelease/39250.wss
I recommend reading the comments on the New York Times article. My favorite comment so far is:
MC - NYC
The Singularity edges closer...
Haven't found the actual paper, yet, but I think it's "High-density integration of carbon nanotubes via chemical self-assembly" as mentioned here: http://researcher.watson.ibm.com/researcher/view_pubs.php?person=us-aaronf&t=1
Can't wait for marketing to get involved, changing high-density carbon nanotube transistors (CNTs) into carbon ultra-nanotube transistors.
IBM marketing will never approve a 4 letter acronym when a 3 letter acronym will suffice. ( Deadpan humor mode set on full. )
article text:
Carbon nanotubes have potential in the development of high-
speed and power-efficient logic applications1–7. However, for
such technologies to be viable, a high density of semiconduct-
ing nanotubes must be placed at precise locations on a sub-
strate. Here, we show that ion-exchange chemistry can be
used to fabricate arrays of individually positioned carbon nano-
tubes with a density as high as 1 3 109cm22—two orders of
magnitude higher than previous reports8,9. With this approach,
we assembled a high density of carbon-nanotube transistors in
a conventional semiconductor fabrication line and then electri-
cally tested more than 10,000 devices in a single chip. The
ability to characterize such large distributions of nanotube
devices is crucial for analysing transistor performance, yield
and semiconducting nanotube purity.
The precise placement of carbon nanotubes on a substrate typi-
cally involves one of three techniques: the direct growth of nano-
tubes on a substrate10,11, the transfer of nanotubes from a ‘growth’
substrate to a device substrate5,6, or the deposition of nanotubes
from solution onto a device substrate8,9,12–18. Because nanotubes
can be metallic or semiconducting, a further consideration for
high-performance digital logic is the degree to which metallic nano-
tubes can be eliminated. Although approaches for enriching sub-
strate-supported semiconducting nanotubes during or after
synthesis have been demonstrated19,20, currently the most effective
techniques involve processing the nanotubes in solution21.
One promising approach for placing solution-based nanotubes is
to selectively position them on a specific substrate by chemically
functionalizing the nanotubes or the substrate14–18. This typically
involves using a patterned surface (such as SiO2/HfO2) such that
nanotubes deposited from solution adhere only to one part of the
pattern (the HfO2, for example). Key metrics for determining
the efficacy of the deposition are the density of individually
placed nanotubes, which must exceed 1 × 1010cm22, with a pitch
smaller than 10 nm for high-performance logic6,7, and the selectiv-
ity, which is the degree to which adsorption takes place only on the
pattern of interest. In general, however, solution-based approaches
that result in high density exhibit poor selectivity14,16, and those
that offer high selectivity have low density17,18.
We have developed a selective placement method based on ion
exchange between a functional surface monolayer and surfactant-
wrapped carbon nanotubes in aqueous solution. Strong electrostatic
interaction between the surface monolayer and the nanotube surfac-
tant leads to the placement of individual nanotubes with excellent
selectivity and a density of 1 × 109cm22. Furthermore, the
approach is compatible with the most efficient solution-based sep-
aration schemes21, allowing wafer-scale integration using highly
purified carbon nanotubes.
Our nanotube placement using an ion-exchange technique
is illustrated in Fig. 1a. The surface monolayer is formed from
4-(N-hydroxycarboxamido)-1-methylpyridinium iodide (NMPI)
molecules, which were synthesized from commercially available
methyl isonicotinate (see Methods). The monolayer contains a
hydroxamic acid end group that is known to self-assemble on
metal oxide surfaces, but not on SiO2(refs17,18,22). We selectively
self-assembled NMPI on HfO2regions of a patterned SiO2/HfO2
surface. The functionalized surface was then placed in an aqueous
solution of carbon nanotubes. Solubility of the nanotubes was
achieved using an anionic surfactant (sodium dodecyl sulphate,
SDS). Excess surfactant in the solution was removed by dialysis.
The anion of NMPI (that is, iodide) is exchanged with the
anionic surfactant wrapped around the nanotubes, leading to a
strong coulombic attraction between the negatively ch
There's some info here on Nature but it's pay walled
http://www.nature.com/nnano/journal/vaop/ncurrent/full/nnano.2012.189.html
There's some additional info in a pdf from the same site here
http://www.nature.com/nnano/journal/vaop/ncurrent/extref/nnano.2012.189-s1.pdf
Watch those corners
Ars also has a piece on this, here.
-- Cheers!
Yes.
Actually, no. Micro-architecture could continue to evolve without die shrinks (likely toward a proliferation of specialized units) and software could also evolve. Probably both for a decade or so, before the shrink stall becomes a fed stall. A feature of Moore's Law rarely expressed is that software lags architecture, and architecture lags die size.
I realized a long time ago that if I could gain a 50% speed increase by rewriting a critical application loop in assembly language, it generally wasn't worth the bother. The next processor architecture would mess up you clever clock-count calculations. The effort was almost always better invested in satisfying feature demand as PCs became more capable. Not only does the architectures improve, but so does the cleverness of your compiler (not including your hand-polished asm). If the software people actually knew that die shrinks were a thing of the past, it would make sense to be more aggressive in the choice of algorithms and execution regimes. They might even be well paid to indulge in premature optimizations postponed, since this would become the main avenue to sustaining performance gains.
There might be more pressure to bet on the right horse, which could thin the herd. Competence gradients tend to have this effect.
"IBM has apparently made a breakthrough..." They either have or haven't made breakthrough. "Apparently" doesn't really cut it I'm sorry
Well, at such a small scale, everything is controlled by quantum mechanics. Oh, excuse me: everything at such small scale may or may not controlled by quantum mechanics.
Ezekiel 23:20
Do you have any evidence of IBM doing this? Ever?
If it's paywalled, don't even fucking bother to link it, most of us will naturally avoid the link.
If you can't find a non-paywalled version, then don't bother at all.
Still waiting on Serviscope_minor to wake up to fucking reality and realize that Jessica Price isn't going to fuck him.