Experimental Port of Debian To OpenRISC
Via Phoronix comes news that Debian has been ported to the OpenRISC architecture by Christian Svensson. Quoting his mailing list post:
"Some people know that I've been working on porting Glibc and doing some
toolchain work. My evil master plan was to make a Debian port, and today
I'm a happy hacker indeed! ... If anyone want to try this on real hardware (would be very cool to see how
this runs IRL), ping me on IRC [#openrisc on freenode] and I'll set you up with instructions how to
use debootstrap - just point to a repo with the debs and you're all set,
the wonders of binary distributions."
For those who don't know, OpenRISC is the completely open source RISC processor intended as the crown jewel of the Opencores project. A working port of glibc and a GNU/Linux distribution is a huge step toward making use of OpenRISC practical. There's a screencast of the system in action, and source on Github (at posting time, it was a month out of date from the looks of it). Christian Svensson's Github account also has repos for the rest of the toolchain.
Without knowing anything about it I'm guessing that or1ksim is a hardware emulator of some kind. What "IRL"hardware can I buy?
very very cool porting debian userspace to a new arch is a fun exercise
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1. Enjoy your job
2. Make lots of money
3. Work within the law
Choose any two.
How is the chip open source if you need a multi-billion dollar plant to make computer processors of any kind?
Guys! Look at TFS!
Really look at it!
The post... EXPLAINS WHAT OPENRISC IS!
Is this /.?
Computer processors may be made gears, vacuum tubes, and transistors. There were computers before the IC....
If a RISC design is simple enough someone with enough patience could make a low clock speed implementation out of transistors / logic gates / minecraft redstones... This has been done recently for some 8 bit CPU's that started life as IC's and there is whole generation of "mainframes" made this way before the IC.
In a few years , just as with 3d printer movement, there could be
Note: The ARM(2) CPU is 30'000 transistors and a RISC design.
You don't need a multi-billion dollar plant to make the processors. You just need to pay someone who does. You can get small quantities of ASICs made for around $2-5k by taking advantage of programs that put many designs from different people on the same wafer.
Point is that since the chip's HDL models are available, w/o any legal restrictions, theoretically, any company w/ a multi-billion dollar fab can take the design, tape and fab it out using those models. In practice, such a company would have to hire its own design, device, process and product engineers to actually produce such a chip. But their designers would essentially have to tweak the designs to the process to meet certain spec parameters, not to build the CPU at gate level from scratch.
This is sort of the point w/ open source hardware, just like w/ open source software. Open source software doesn't actually have to be good or even necessarily work - it just has to be open, but getting it to work and work well is one of the long term visions that the model is supposed to support. This is even truer about open source hardware. Theoretically, any number of fabs can take the OpenRISC HDLs and try spinning out chips based on that. In reality, anyone who really wants to do a good job there would have to hire the engineers needed to actually make it work.
One thing I wonder about at hardware level - let's say the HDL code has been tweaked for process variations: does that have to be published, as per the GPL? I can see that being a showstopper - why should any fab publicly publish internal process defects or issues, which could be used by competitors to calculate their real costs? I would imagine that to be the main reason why no foundry company has chosen to take OpenRISC and make a CPU w/ its HDL code - why take that risk?
OpenRISC is a brand name, much like ARM.
It consists of two main ISA's. A 32 and 64 bit with vector instruction extensions isa's.
The first and so far only implementation in verilog is called OR1200 using the 32bit isa.
I did an evaluation of the CPU over 10 years ago. It was the first implementation and by all standards of CPU design it was crap then and still is. The SPARC Leon is a infinitely better alternative.
Hi, Having worked on the OpenRISC project for ~4 years I thought I could share some insights here, as the licensing question pops up all the time. The RTL for OpenRISC and most of the peripheral controllers that are used are licensed under LGPL, not GPL. While we all know that this is a software license with some concepts that don't translate well to hardware, the consensus is that LGPL means that you are obliged to shared modifications of the LGPL-licensed core, while GPL-licensed RTL would require the whole SoC to be GPL.
This is a view that we in the OpenRISC community share with the Open Source Hardware developers at CERN and other groups. This has also been tried by IP lawyers for a large company that wanted to use OpenRISC about ten years ago.
As for ASIC implementations it could be worth mentioning that there are ASICs running or1200 (the original LPGL-licensed OpenRISC implementation) in Samsung Digital TVs, in some of the Allwinner SoCs, Zigbee ASICs and other places, so it has been done many times over the years