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OpenRISC Gains Atomic Operations and Multicore Support
An anonymous reader writes "You might recall the Debian port that is coming to OpenRISC (which is by the way making good progress with 5000 packages building) — Olof, a developer on the OpenRISC project, recently posted a lengthy status update about what's going on with OpenRISC. A few highlights are upstreamed binutils support, multicore becoming a thing, atomic operations, and a new build system for System-on-Chips."
RTFA.
With a single core, it worked without atomic operations (albeit non-optimal. But then, which CPU is optimal?).
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> Absolutely nothing over any of the well supported and understood open source MIPS implementations.
Ah! Read this ( http://jonahprobell.com/lexra.... ) and be cautious when re-implementing the MIPS ISA..
What are the advantages of openrisc?
It is free, so if you want to run a softcore, there are no license fees. If you can read Verilog, you can verify that there are no NSA backdoors.
What are the performance of such a softcore?
An FPGA softcore is going to run several times slower, and consume several times as much power, as a hardcore. If you need a small amount of computing, and most of your app is in the FPGA fabric, then that is reasonable, although you might be able to get by with an 8-bit softcore like PicoBlaze, or even roll your own mini 8-bit core with opcodes customized for your app (this is not that hard, and is a fun project if you are learning Verilog and ready to go beyond blinking LEDs). But if you are doing something compute intensive, you may want to look for something with an integrated hardcore.
Can I expect to have something usable?
That depends on what you are using it for.
MIPS may (or may not be) "open source", however it is not free to implement. Implement the latest MIPS ISA without a license agreement from MIPS and you'll be sued to smithereens. You won't be sued if you implement OpenRISC though.
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6502! Just kidding.
Mostly random stuff.
It is also possible to use the Verlog to make an ASIC if you go into production.
See my blog http://ilovecookes.blogspot.com/ for light hearted technical information.
" This is just another cause-we-can hobby project on the front page of Slashdot."
OpenRISC is far from a "cause-we-can" project.
6502! Just kidding.
1 Accumulator and 2 Index Registers. Can't get more optimal than that!
The original 6502 had atomic operations. Read-modify-write operations on memory, such as bit shifting or adding or subtracting 1, would execute a read-write (old value)-write (new value) sequence. This protocol of not waiting between a read of a particular address and writing the new value would allow a memory controller to lock the bus by allowing only one device to write at once. This feature was removed in 65C02 in favor of read (and use)-read (and ignore while calculating)-write (new value), which is slightly safer for memory-mapped I/O but possibly less safe for synchronizing a CPU with other CPUs or DMA sources.
oh? what problem does it solve?
If you can read Verilog, you can verify that there are no NSA backdoors.
But is there a backdoor in your Verilog compiler? Normally, you might use David A. Wheeler's diverse double-compiling method to ensure beyond reasonable doubt that your compiler isn't backdoored. But diverse double-compiling doesn't work unless the compiler is written in the same language that it compiles. And I don't think the Verilog compiler is written in Verilog.
you might be able to get by with an 8-bit softcore like PicoBlaze
Wikipedia's article about PicoBlaze states that it's not free to use on anything but a Xilinx FPGA. So if you switch to Altera or go into production with an ASIC, you might have to switch to PacoBlaze and deal with any minor behavior differences.
"roll your own mini 8-bit core with opcodes customized for your app (this is not that hard"
Not that hard by Verilog standards. The sight of it tends to make software developers run in terror.
Or to be clearer, MIPS owns several patents on instructions in the ISA. Though I think some of them were worked around another way since the patent covers implementation.
But many other architectures are patented as well - x86 is covered by many patents (most owned between AMD and Intel and cross-licensed), which probably explains why a good chunk of embedded x86 only do the i486 ISA. (Excepting companies like Via who license the patents).
Does anyone have any idea why OpenRISC is big-endian? Considering that little-endian has pretty much won nowadays (Every major CPU is either little or bi endian) why would anyone want to release a big-endian cpu?
Another advantage of an open source softcore, is that you can add your own application specific opcodes. You could run your app in a profiler with the standard instruction set, and identify the hot spots. If a big chunk of your CPU time is spent in a single tight loop, you could implement that code directly in FPGA fabric, and execute each iteration in a single clock tick with a custom instruction. For instance, lets say you need to run some sort of CRC or crypto, with involves shifting, masking and adding bits. That would be easy to code up in Verilog into a single instruction, which is then executed by extending OpenRisc for the new opcode. Then just use the "asm" feature of GCC to put that opcode in the inner loop of your C program. Depending on your app, it is possible that you could get better performance from a customized softcore than from a generic hardcore, like ARM or MIPS.
We're just about to open source (Apache-style license) our MIPS IV implementation. MIPS IV is over 20 years old, so there exists at least one implementation that is not covered by any patents. We can't guarantee that nothing in our implementation is patented, but the patents in your linked article have all expired now.
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You really don't need atomic operations until you get into multi-core programming (this is so that you are guaranteed to instantly change a value before another core reads/writes to it). Even the C++ standard doesn't guarantee atomic operations unless you explicitly declare a variable atomic.
>The sight of it tends to make software developers run in terror. That's because it has very little to do with software programming.
Is this free to implement?
And those patents, or more specifically the single patent about the unaligned load and store instructions on MIPS expired years ago. To be specific it expired in December 2006.
So while the patent was an issue back in ~200 when OpenRISC was launched it is no longer relevant, and you would be better off implementing a MIPS32 and MIPS64 bit core.
I would also point out that there are full open source implementations of the SPARC architecture, which never suffered from the patent problems of MIPS.
"oh? what problem does it solve?"
What the fuck is so hard to understand here? The answer is in the name of project: An opensource CPU core. There, was that so hard?
Besides being a snarky ass, what was the point of your post? It sounds as if you would rather spark a flame war rather than do some actual research which would take oh lets say 5-10 minutes.
There are other open source cores but none of them are trying to provide a full blown CPU core that could potentially be used for mobile or desktop use. Most of them are for embedded use and are little more than a micro controller and lack an MMU.
From the blog post linked in the article:
"the requirement for implementing a mutex is that an mutex operation is never allowed to be interrupted. Previously on OpenRISC this was done by making a syscall that disabled all interrupts as it's first instructions."
You have not even answered the question with all your ranting and hot air. Again, what problem does an open source CPU format solve? I cannot think of a one, my open source software works fine on x86, sparc, MIPS, ARM7 (and anyone interested can get the specs for most of those architectures). I'll even make a claim that open specs are good enough for a CPU, irrelevant whether the particular mask patterns are known.
yes, you do. in a preemptable OS, in a multi-threaded app, you need atomic operations to share data between threads, as any read-modify-write operation on shared data gets wrecked when it is preempted between the read and the write.
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Exactly. This is very much a hardware thing - and if you want a processor embedded in your chip, it's because you want to run software. Spending time messing around with intricate hardware design is just going to divert you from the important tasks.
yes, you do. in a preemptable OS, in a multi-threaded app, you need atomic operations to share data between threads, as any read-modify-write operation on shared data gets wrecked when it is preempted between the read and the write.
Furthermore, what is atomic in terms of context switching preemption is not necessarily atomic in terms of memory bus arbitration. The two can usually coincide, but they don't have to.
I would also point out that there are full open source implementations of the SPARC architecture, which never suffered from the patent problems of MIPS.
...but they do suffer from (a very poor implementation of) register windows.
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For a sufficiently complex netlist, how can you prove that the HDL compiler didn't insert an obfuscated backdoor? This is especially important if one of the HDL compiler's developers placed highly in an Underhanded C Contest.
Actually I found the atomic ll/sc stuff to be convenient even with multiple tasks on a single processor, as it means no need to lock out context switching for atomic operations.
Even with just a single core in the processor you will still hit concurrency issues if there are other processors in the system sharing some resource.
What about multi-processor systems that share memory? It's not multi core if each processor only has one core.
Which can be slow and clumsy though, often a bad choice to use for real time systems.
How about embedding a CPU core into your ASIC design, without paying licensing fees to MIPS or ARM?
CAS is an atomic instruction, probably even more atomic than the stuff in OpenRISC (which uses a load-exclusive/store-conditional pair of instructions, similar to many RISC machines).
We're using about 30% of a Stratix IV, a bit more with an FPU. We've also got a smaller version (no TLB, smaller caches) and multicore / multithreaded variants that are larger. We run at 100MHz (pass timing at 120-150MHz depending on the features enabled, but 100MHz gives some headroom when experimenting).
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and for a couple bucks you can buy an 8 or 16 bit cpu and slap on on a board with your custom FPGA, you're doing it wrongly.
eh, most of my life was engineering physical things including controllers. You take a couple buck CPU and slap it on a board with your FPGA, in 99.9999% of cases making your on fucking CPU is a waste of time and money. It's like a developer who says "I need to write my own web server from scratch to run my php code"
And yet we have multiple open source web servers, each with varying levels of complexity, feature sets and usage cases.
yes, that would be one way to implement atomic operations
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