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OpenRISC Gains Atomic Operations and Multicore Support
An anonymous reader writes "You might recall the Debian port that is coming to OpenRISC (which is by the way making good progress with 5000 packages building) — Olof, a developer on the OpenRISC project, recently posted a lengthy status update about what's going on with OpenRISC. A few highlights are upstreamed binutils support, multicore becoming a thing, atomic operations, and a new build system for System-on-Chips."
RTFA.
With a single core, it worked without atomic operations (albeit non-optimal. But then, which CPU is optimal?).
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> Absolutely nothing over any of the well supported and understood open source MIPS implementations.
Ah! Read this ( http://jonahprobell.com/lexra.... ) and be cautious when re-implementing the MIPS ISA..
What are the advantages of openrisc?
It is free, so if you want to run a softcore, there are no license fees. If you can read Verilog, you can verify that there are no NSA backdoors.
What are the performance of such a softcore?
An FPGA softcore is going to run several times slower, and consume several times as much power, as a hardcore. If you need a small amount of computing, and most of your app is in the FPGA fabric, then that is reasonable, although you might be able to get by with an 8-bit softcore like PicoBlaze, or even roll your own mini 8-bit core with opcodes customized for your app (this is not that hard, and is a fun project if you are learning Verilog and ready to go beyond blinking LEDs). But if you are doing something compute intensive, you may want to look for something with an integrated hardcore.
Can I expect to have something usable?
That depends on what you are using it for.
MIPS may (or may not be) "open source", however it is not free to implement. Implement the latest MIPS ISA without a license agreement from MIPS and you'll be sued to smithereens. You won't be sued if you implement OpenRISC though.
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6502! Just kidding.
Mostly random stuff.
6502! Just kidding.
1 Accumulator and 2 Index Registers. Can't get more optimal than that!
The original 6502 had atomic operations. Read-modify-write operations on memory, such as bit shifting or adding or subtracting 1, would execute a read-write (old value)-write (new value) sequence. This protocol of not waiting between a read of a particular address and writing the new value would allow a memory controller to lock the bus by allowing only one device to write at once. This feature was removed in 65C02 in favor of read (and use)-read (and ignore while calculating)-write (new value), which is slightly safer for memory-mapped I/O but possibly less safe for synchronizing a CPU with other CPUs or DMA sources.
"roll your own mini 8-bit core with opcodes customized for your app (this is not that hard"
Not that hard by Verilog standards. The sight of it tends to make software developers run in terror.
Another advantage of an open source softcore, is that you can add your own application specific opcodes. You could run your app in a profiler with the standard instruction set, and identify the hot spots. If a big chunk of your CPU time is spent in a single tight loop, you could implement that code directly in FPGA fabric, and execute each iteration in a single clock tick with a custom instruction. For instance, lets say you need to run some sort of CRC or crypto, with involves shifting, masking and adding bits. That would be easy to code up in Verilog into a single instruction, which is then executed by extending OpenRisc for the new opcode. Then just use the "asm" feature of GCC to put that opcode in the inner loop of your C program. Depending on your app, it is possible that you could get better performance from a customized softcore than from a generic hardcore, like ARM or MIPS.
We're just about to open source (Apache-style license) our MIPS IV implementation. MIPS IV is over 20 years old, so there exists at least one implementation that is not covered by any patents. We can't guarantee that nothing in our implementation is patented, but the patents in your linked article have all expired now.
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And those patents, or more specifically the single patent about the unaligned load and store instructions on MIPS expired years ago. To be specific it expired in December 2006.
So while the patent was an issue back in ~200 when OpenRISC was launched it is no longer relevant, and you would be better off implementing a MIPS32 and MIPS64 bit core.
I would also point out that there are full open source implementations of the SPARC architecture, which never suffered from the patent problems of MIPS.
From the blog post linked in the article:
"the requirement for implementing a mutex is that an mutex operation is never allowed to be interrupted. Previously on OpenRISC this was done by making a syscall that disabled all interrupts as it's first instructions."
yes, you do. in a preemptable OS, in a multi-threaded app, you need atomic operations to share data between threads, as any read-modify-write operation on shared data gets wrecked when it is preempted between the read and the write.
Furthermore, what is atomic in terms of context switching preemption is not necessarily atomic in terms of memory bus arbitration. The two can usually coincide, but they don't have to.
Actually I found the atomic ll/sc stuff to be convenient even with multiple tasks on a single processor, as it means no need to lock out context switching for atomic operations.
Even with just a single core in the processor you will still hit concurrency issues if there are other processors in the system sharing some resource.