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Intel To Offer Custom Xeons With Embedded FPGAs For the Data Center
MojoKid (1002251) writes For years, we've heard rumors that Intel was building custom chips for Google or Facebook, but these deals have always been assumed to work with standard hardware. Intel might offer a different product SKU with non-standard core counts, or a specific TDP target, or a particular amount of cache — but at the end of the day, these were standard Xeon processors. Today, it looks like that's changing for the first time — Intel is going to start embedding custom FPGAs into its own CPU silicon. The new FPGA-equipped Xeons will occupy precisely the same socket and platform as the standard, non-FPGA Xeons. Nothing will change on the customer front (BIOS updates may be required), but the chips should be drop-in compatible. The company has not stated who provided its integrated FPGA design, but Altera is a safe bet. The two companies have worked together on multiple designs and Altera (which builds FPGAs) is using Intel for its manufacturing. This move should allow Intel to market highly specialized performance hardware to customers willing to pay for it. By using FPGAs to accelerate certain specific types of workloads, Intel Xeon customers can reap higher performance for critical functions without translating the majority of their code to OpenCL or bothering to update it for GPGPU.
Intel Xeon customers can reap higher performance for critical functions without translating the majority of their code to OpenCL or bothering to update it for GPGPU
In other words, to help prevent people from buying AMD and nVidia products.
No ignore that entire last sentence, it's dumb. FPGAs don't do floating point very well for one and even their integer performance will never rival a GPGU either in performance, or power. For another, I can and do, use both FPGAs and OpenCL/GLSL in my daily life and would infinitely prefer to port my functions to OpenCL over an FPGA. It's quite a bit more work to synthesize and validate an FPGA design than it is to write OpenCL code and debug the usual way.
I think it's far more likely customers are implementing custom hardware solutions using the FPGA related to power management, server management and datastructure infrastructure that can only be done with an FPGA in certain power domains. I say this having designed servers and dealt with the feature requests.
My guess would be that the real perk is bandwidth and latency. Unless Intel really phones it in on integration, the FPGA should have about the fastest, lowest-latency, link to the CPU, possibly even some of the cache, especially if they throw in a big chunk of eDRAM, as they have for 'Iris Pro' parts, that money can buy.
Less of a "Hey, let's do this instead of GPU compute!" and more of a "It sucks that our weirdo application-specific operation is probably never going to be one of Intel or AMD's extensions to x86; but this is the closest we can get to having it added" thing.
LOL. But they will have to translate it to Verilog or VHDL, which is far harder.
I suppose it depends on your skill set, but I find Verilog to be much easier than coding GPU pipelines. You just need to realize that you are not coding a program that will be sequentially executed, but a hardware description where everything happens at once. Anyway, these chips sound really slick, and I would definitely pay for a PC containing a CPU with some FPGA fabric instead of a standard X86.
FPGAs don't do floating point very well for one and even their integer performance will never rival a GPGU either in performance, or power.
Sure, and a hammer makes a terrible screwdriver. GPUs are specifically designed for register-to-register SIMD operations, so of course they are going to excel at that. But an FPGA is going to be better at bitstream operations, including many hashing and encryption algorithms.
My guess would be that the real perk is bandwidth and latency. Unless Intel really phones it in on integration, the FPGA should have about the fastest, lowest-latency, link to the CPU, possibly even some of the cache, especially if they throw in a big chunk of eDRAM, as they have for 'Iris Pro' parts, that money can buy.
As usual, the slashdot post has the absolute worst story link. compare http://www.enterprisetech.com/... which gives you links to where it gets its info, namely https://communities.intel.com/... and http://gigaom.com/2014/06/18/i... ... the latter is the interesting link because it tells us that the FPGA will have access to main memory. I personally would presume that means it's tied into the memory controller somehow.
Less of a "Hey, let's do this instead of GPU compute!" and more of a "It sucks that our weirdo application-specific operation is probably never going to be one of Intel or AMD's extensions to x86; but this is the closest we can get to having it added" thing.
What I began fantasizing about immediately upon reading the article was some sort of optimizer that would semi-automatically build functional units to perform whatever function the CPU was grinding on at the moment, with some sort of recognition engine and periodic updates garnered from participating customers to help special-yet-common cases. As well, seeing how customers actually use FPGA with their products will help Intel decide what functionality to add to their next (or next+1, etc) processor.
There are already options to add an FPGA to your Xeon system, with its own blob of RAM. Since they talk about this being fundamentally different, I'm not sure what makes sense except the idea of it being connected at the memory controller. Hopefully there will be a talk with some nice block diagrams released soon.
"You're right," Fisheye says. "I should have set it on 'whip' or 'chop.'"
I have a friend in that in graduate school used a motherboard that could take an Altera FPGA in one of the Xeon sockets. This seems like the next logical step; hopefully it's not too expensive so that the hardware is accessible to hobbiest/engineers. I am happy that both Xilinx and Altera offer cheap development boards so that we can play with the new offerings. It's easier to convince a boss to use it if we're familiar with it. (hint hint, wry grin)
I use the zynq processor at my job, and am very happy with the amount of flexibility you can get out of an embedded system having access to the FPGA and processor fabric; you can directly access gigasample ADC's, etc. When I first got into embedded systems on an FPGA, the processor was a soft-IP and not terribly fast. Both Xilinx and Altera now offer ARM processors that run up to 1GHZ. The amount of system flexibility is great. You can make major architectural choices without changing the hardware. You might have a data-path, or computation that is simply too intensive for a processor to handle.. You have the flexibility to port this portion to the logic side. If you're in a rapid prototyping mode and are constrained by board size and mechanical packaging constraints, FPGAs are great.
Debugging SoC still has it's challenges though. It's easy to program FPGAs, and easy to program the microprocessor. The tools are still a little clunky from Xilinx or Altera to handle their hybrid SoC parts. There is still work to be done to make them work more seamlessly.
Intel has already come up with an Atom CPU with integrated FPGA, but only for the embedded market.
I'd already been thinking about the possibility of end-user-accessible, on-the-fly-reprogrammable FPGA functionality as part of a "regular" computer before I heard Intel had produced an integrated CPU/FPGA (though it's not clear how easily configurable the FPGA was there). I raised the issue in that previous thread and got a *very* interesting and informative response (thank you Tacvek) that pointed out some major problems with the concept of general access to such functionality.
The issues raised there explain why Intel are unlikely to be making an easily-reconfigurable hybrid product like this available to the general public any time soon, however smart and exciting the idea sounds.
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