Will 7nm and 5nm CPU Process Tech Really Happen?
An anonymous reader writes "This article provides a technical look at the challenges in scaling chip production ever downward in the semiconductor industry. Chips based on a 22nm process are running in consumer devices around the world, and 14nm development is well underway. But as we approach 10nm, 7nm, and 5nm, the low-hanging fruit disappears, and several fundamental components need huge technological advancement to be built. Quoting: "In the near term, the leading-edge chip roadmap looks clear. Chips based on today's finFETs and planar FDSOI technologies will scale to 10nm. Then, the gate starts losing control over the channel at 7nm, prompting the need for a new transistor architecture. ... The industry faces some manufacturing challenges beyond 10nm. The biggest hurdle is lithography. To reduce patterning costs, Imec's CMOS partners hope to insert extreme ultraviolet (EUV) lithography by 7nm. But EUV has missed several market windows and remains delayed, due to issues with the power source. ... By 7nm, the industry may require both EUV and multiple patterning. 'At 7nm, we need layers down to a pitch of about 21nm,' said Adam Brand, senior director of the Transistor Technology Group at Applied Materials. 'That's already below the pitch of EUV by itself. To do a layer like the fin at 21nm, it's going to take EUV plus double patterning to round out of the gate. So clearly, the future of the industry is a combination of these technologies.'"
Could someone explain to me why further refinement of fabrication process is the only way to progress? With a car analogy?
Clearly e-beam has some serious issues (throughput, to name one...), but progress is being made on that front. For instance, http://www.mapperlithography.c... ( http://nl.wikipedia.org/wiki/M... -- though it appears there's only a Dutch entry...).
We're already at the point where 22nm components are more expensive per transistor than those at 28nm.
Previous shrinks lowered the cost of each transistor. It doesn't look like it's going to happen after 28nm.
Then IBM would saddle it with some really complex, bloated, crappy middleware called "WebSphere Atomic Appliance for Business". It would be more expensive and run slower than a no-name Intel based blade running Linux and an open source framework. You'd need their professional services to manage it for you.
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I'd say the low-hanging fruit disappeared a few decades ago. Continuing down the feature size curve has for many years required a whole slew of every-more-complicated tricks and techniques.
That said: yes, going forward is going to be increasingly difficult. You will eventually reach an insurmountable limit that no amount of trickery or technology will be able to overcome. I predict it'll be somewhere around the 0 nm process node.
I worry about the reliability with tinyer and tinyer CPU feature size. ...how will those CPUs be doing, reliability-wise, 10yrs later?
When I buy something 'expensive', I expect it to last at least 10yrs, and CPUs are kinda expensive, to me.
(I still have an Athlon Thunderbird 700MHz Debian workstation that I use, for example, and it's still reliable.)
Uh, Linux geek since 1999.
Perhaps, but at least with lithography you can do it across the entire wafer (or die) area in a single go. That's batch processing all the transistors at once, rather than serially processing them with AFM.
There is a limit we'll hit eventually, we're approaching circuits that are single digit atoms wide. No matter what we'll never get a circuit less than a single atom. Don't get me wrong, I don't think 10nm is going to be the problem but somewhere around single digit atoms wide we're going to run out of options to make them smaller.
Kind of. Heat dissipation starts being a bigger problem, and thermally limit slock speed. Look at overclocking sandy bridge vs ivy bridge chips.
I read an article in the Apple ][ days claiming going beyond 16MHz was impossible, given track to track inductance.
I should use this sig to advertise my book ISBN-13 : 978-1501515132.
There is a limit we'll hit eventually, we're approaching circuits that are single digit atoms wide. No matter what we'll never get a circuit less than a single atom.
We'll go optical, and we'll use photons...
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There are a number of factors that affect the value of technology scaling. One major one is the increase in power density due to the end of supply and threshold voltage scaling. But one factor that some people miss is process variation (random dopant fluctuation, gate length and wire width variability, etc.).
Using some data from ITRS and some of my own extrapoliations from historical data, I tried to work out when process variation alone would make further scaling ineffective. Basically, when you scale down, you get a speed and power advantage (per gate), but process variation makes circuit delay less predictable, so we have to add a guard band. At what point will the decrease in average delay become equal to the increase in guard band?
It turns out to be at exactly 5nm. The “disappointing” aspect of this (for me) is that 5nm was already believed to be the end of CMOS scaling before I did the calculation. :)
Incidentally, if you multiply out the guard bands already applied for process variation, supply voltage variation, aging, and temperature variation, we find that for an Ivy Bridge processor, about 70% of the energy going in is “wasted” on guard bands. In other words, if we could eliminate those safety margins, the processor would use 1/3.5 as much energy for the same performance or run 2.5 times faster in the same power envelope. Of course, we can’t eliminate all of them, but some factors, like temperature, change so slowly that you can shrink the safety margin by making it dynamic.
You'd think so, but the problem is global interconnect. Not gates. It was all the way back at the 250nm node when interconnect and gate delay were about the same.
At the 28nm node, wire delay is responsible for something like 80% of the time it takes for signals to work their way through a circuit.
And it some cases inverters are actually used to help signals propagate more quickly down long wires. In other words, long wires are so slow compared to gates that adding gates can speed things up!
An interesting article here discribes the horrendiously difficult challenges that face EUV:
https://www.semiwiki.com/forum...
The problem is that memristance effects begin to manifest below 5nm
Thus, start using memristors to build IMP-FALSE logic circuits.
The problem with stacking is the thermal/power situation. Specifically, how much power can a processor use before it's impractical to power and cool it? And when you have two or more processor dies stacked on top of eachother, the heatsink is only going to contact the topmost one. How do you remove that heat from the bottom one?
I suspect the answers to those questions are, it's not practical to use that much more power that we use in high-end desktop chips today (150-200W is probably the limit of practicality), and I recall some interesting stuff from IBM years ago where they were building vertical cooling channels into CPU dies to handle stacking, so that the heat could be moved from lower dies up to where it could be removed.
Perhaps the approach could be going with CPU designs that optimize for power consumption rather than performance (but still more efficient, consuming less power per unit of work), and then stack a bunch of them.
And this little tidbit I'm sure has CPU OEMs scared....they passed "good enough" on their designs and went so far into "insanely overpowered" that consumers really have no reason to buy before the previous unit dies.
Take what I'm typing on as an example, its an HP Pro 3000 which since it came with Vista (which I of course upgraded to Win 7, putting 32bit Vista on a PC with 4GB? WTH HP?) I would date it around 07-08. It has a Pentium Dual at 2.7Ghz, 4GB of RAM, and a 500GB HDD....how many home users are actually gonna be able to max this out? I pound the shit out of this machine, downloading drivers and burning discs and yanking data off of memory cards, often at the same time, and it just purrs, so why buy a new one? Now we are seeing the same thing with ARM, my dad recently picked up a tablet I recommended which has 4 cores, 1GB of RAM and 8GB of onboard storage, final cost? $140 shipped, the odds that he will be able to max it out? pretty much zero. this thing has enough power it can easily drive his widescreen TV over HDMI, surf, chat, and gets great battery life...what motivation does he have to buy a new one?
Lets face it X86 systems have become like washers and dryers, no need to get a new before the old one dies. Hell this is even true for gamers, my gaming PC at home is fricking 5 years old now which is ancient history in the PC world yet with a hexacore, 8GB of RAM, and 3TB of HDD space the only thing I've had to do since buying it is upgrade my GPU. That's it, that is all I've had to do and I'm playing Bioshock Infinite and Far Cry 3 and anything else i want to play with plenty of bling and decent framerates. We are seeing X86 play out on fast forward with ARM now going up to octocore because MHz bumps are getting harder to do without blowing the power budget, there is just no reason to buy before the current one dies which I'm sure is scarier than trying to hit 14nm to Intel and TSMC.
ACs don't waste your time replying, your posts are never seen by me.
I remember the 90's too and I don't remember any of that.
The race to 1 GHz were heady, optimistic days, and I don't recall anyone thinking that once we got there, it would all be over.
So I call bullshit on your post.
Yeah but I also remember an article saying that the universal speed limit is 300,000 km/hr and that one seems to have held up. There is a physical limit at some point.
You do realize that we've been in that situation since the dawn of computers, don't you? Once we get close to filling needs, people come up with other needs. Once processor development more or less stalls out, people will still want better performance, but they won't get it by updating their systems any more. Software development is a pretty secure profession.
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