New Network Design Exploits Cheap, Power-Efficient Flash Memory
jan_jes writes: The researchers at MIT were able to make a network of flash-based servers competitive with a network of RAM-based servers by moving a little computational power off of the servers and onto the chips that control the flash drives. Each server connected to a FPGA and each FPGA, in turn, was connected to flash chips and to the two FPGAs nearest it in the server rack. As it is connected to each other, they created a very fast network that allowed any server to retrieve data from any flash drive. Finally, the FPGAs executed the algorithms that preprocessed the data stored on the flash drives.
FPGA is just gimmicked flash sandbagged with a liberal topping of patents. The fundamental patents are getting long in the tooth, keep an eye on those expiry dates. See the obvious connection with OP.
When all you have is a hammer, every problem starts to look like a thumb.
Through in 4 gigs of ram, too!
The law is a weapon of the government, not a protection for the likes of you. Surely you understand that.
Go back and look at an AS/400, iSeries, i5 and now called IBM i,
Biggest machine I worked on, 32 cores and 3/4TB of ram. And that was still ovly 1/2 as big it could be. But that 3/4TB was not the total ram in the machine, it had IOPs and IOAs that oversaw the the disk drives. Those processors had large ram and were basically fast and faster cache. So our machine with 900 drives in multiple raid-6 groupings (IOPs) with multi-grouping in IOA, acted as a 900 drive raid-0 (stripe) to main core. So reading a file sequencially all the drives will start suppling data first data in 50ms... but then the rest was "just there". Processing 4 billion row history files was easy.
Well, I actually wonder if this isn't something new.
So, think about it, because (I think) this kind of extends a Von Neumann architecture.
It gives you a larger degree of parallelism because all the little doohickies are using their local storage to do some of your tasks.
To me it sounds like they've created something which helps with parallelism on huge data sets.
My guess is your cheap quad core isn't as cheap or suited to these tasks as you think.
Lost at C:>. Found at C.
The EMC Isilon is a cluster of FreeBSD nodes with completely customized filesystem on top. All the nodes are connected to each other by Infiniband, and redundancy is built into OneFS.
I'm visualizing this as someone adding FPGA cards to Isilon nodes, and installing SSDs instead of the usual HDDs in the array. Innovative, but this isn't revolutionary by any means.
The initial academic work to build clusters sharing memory were very similar. They turned into the more modern concepts of NUMA and Snoopy. It is a modification to Von Neumann, but in general this is the way forward now that flash drives are a minimal time hit. It is more about removing unneeded older technology and simplifying the model. Removing some caches, controllers, and drives by using a faster 'memory' while still getting massive storage.
Well FPGAs often do throw in an ARM core or 4 these days:
https://en.wikipedia.org/wiki/Field-programmable_gate_array
e.g. the A Xilinx Zynq-7000 includes a Dual Core Cortex A9 on the chip.
Logic gates are fine, but sometimes you just need some serial execution of code!
Can it run Linux?
Because general purpose processors are slower than a specific purpose module in an FPGA could be. Cheap is not an important consideration in this case.
Be there or be a democrat nerd.
Wow ... No solid states? Sucks to be you, bro!
I art more snarky, and terse than thou. I art Slashdot!
The article explains how it's cost effective and they uses FGPAs contributed by their sponsors.
If they had sponsors to give them free RAM somehow I imagine that would have tipped the price comparison the other direction.
http://lkml.org/lkml/2005/8/20/95
Cheap quad core ARM chips are general purpose and would consume more power than a FPGA. Do you know anything?
Simple: That would not produce papers, PhDs and press-statements.
Most ACs are not even worth the keystrokes to insult them. Be generically insulted by this and ignored otherwise.
Moving some processing out of the central processor and into processors that access storage is not exactly new.
But I bet these servers don't look too terribly much like CDC 6000s. (Especially their FPGA parts.)
The article should be an interesting read. Which I will get to soon, now that I've offered an uninformed opinion about TFA and incidentally exposed my geezerhood.
There's no time like the present. Well, the past used to be.
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Something along those lines -- in a very different era -- were the CDC 6000 series computers designed by Seymour Cray, and their successors.
One or more central processors did the number crunching and general program logic, and some of the OS, with a bunch of smaller, not-so-bright "peripheral processors" doing I/O and certain low-level OS functions. (How not-bright? They couldn't do division or multiplication except by powers of two, for instance.)
Supposedly, Gene Amdahl, designer of the IBM 360 series machines, later said he wished he'd put more smarts into the channel controllers, in the manner of the CDC machines. Don't have a source. That story might be apocryphal, or at least misremembered in its details.
There's no time like the present. Well, the past used to be.
A bottom of the range FPGA - 200 I/O pins, with 216.5 Gb/s for $20.
And the one I have sitting on my desk at the moment has about 500 Gb/s over about 300 pins..
You can't get that on an ARM CPU.